luke
/
nextpnr
mirror of https://github.com/YosysHQ/nextpnr.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

gatemate: implemented remaining PLL features (#1474) 

* gatemate: implemented remaining PLL features

* gatemate: allow longer carry chains
This commit is contained in:
Miodrag Milanović 2025-04-24 09:51:00 +02:00 committed by GitHub
parent c84f20934f
commit bc25b042e9
No known key found for this signature in database
GPG Key ID: B5690EEEBB952194
2 changed files with 13 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
himbaechel/uarch/gatemate/gatemate_util.h
View File

@ -63,7 +63,7 @@ int extract_bits(const dict<KeyType, Property> &ct, const KeyType &key, int star
} }
template <typename T> template <typename T>
std::vector<std::vector<T>> splitNestedVector(const std::vector<std::vector<T>> &input, size_t maxSize = 8) std::vector<std::vector<T>> splitNestedVector(const std::vector<std::vector<T>> &input, size_t maxSize = 32)
{ {
std::vector<std::vector<T>> result; std::vector<std::vector<T>> result;

16
himbaechel/uarch/gatemate/pack.cc
View File

@ -1467,11 +1467,18 @@ void GateMatePacker::pack_pll()
clk = ci.getPort(id_USR_CLK_REF); clk = ci.getPort(id_USR_CLK_REF);
if (clk) { if (clk) {
move_ram_o_fixed(&ci, id_USR_CLK_REF, fixed_loc); move_ram_o_fixed(&ci, id_USR_CLK_REF, fixed_loc);
ci.params[ctx->id("USR_CLK_REF")] = Property(0b1, 1);
if (clk->clkconstr) if (clk->clkconstr)
period = clk->clkconstr->period.minDelay(); period = clk->clkconstr->period.minDelay();
} }
// TODO: handle CLK_FEEDBACK
// TODO: handle CLK_REF_OUT NetInfo *fbk = ci.getPort(id_CLK_FEEDBACK);
if (fbk && !fbk->driver.cell->type.in(id_CC_BUFG))
move_ram_o_fixed(&ci, id_CLK_FEEDBACK, fixed_loc);
if (ci.getPort(id_CLK_REF_OUT))
log_error("Output CLK_REF_OUT cannot be used if PLL is used.\n");
pll_out(&ci, id_CLK0, fixed_loc); pll_out(&ci, id_CLK0, fixed_loc);
pll_out(&ci, id_CLK90, fixed_loc); pll_out(&ci, id_CLK90, fixed_loc);
pll_out(&ci, id_CLK180, fixed_loc); pll_out(&ci, id_CLK180, fixed_loc);
@ -1479,6 +1486,7 @@ void GateMatePacker::pack_pll()
move_ram_i_fixed(&ci, id_USR_PLL_LOCKED, fixed_loc); move_ram_i_fixed(&ci, id_USR_PLL_LOCKED, fixed_loc);
move_ram_i_fixed(&ci, id_USR_PLL_LOCKED_STDY, fixed_loc); move_ram_i_fixed(&ci, id_USR_PLL_LOCKED_STDY, fixed_loc);
move_ram_o_fixed(&ci, id_USR_LOCKED_STDY_RST, fixed_loc);
double out_clk_max = 0; double out_clk_max = 0;
int clk270_doub = 0; int clk270_doub = 0;
@ -1657,7 +1665,7 @@ void GateMatePacker::pack_pll()
// PLL_AUTN - for Autonomous Mode - not set // PLL_AUTN - for Autonomous Mode - not set
// SET_SEL - handled in CC_PLL_ADV // SET_SEL - handled in CC_PLL_ADV
// USR_SET - handled in CC_PLL_ADV // USR_SET - handled in CC_PLL_ADV
// TODO: USR_CLK_REF - based on signals used // USR_CLK_REF - based on signals used
ci.params[ctx->id("CLK_OUT_EN")] = Property(0b1, 1); ci.params[ctx->id("CLK_OUT_EN")] = Property(0b1, 1);
// LOCK_REQ - set by CC_PLL parameter // LOCK_REQ - set by CC_PLL parameter
@ -1666,7 +1674,7 @@ void GateMatePacker::pack_pll()
// CLK180_DOUB - set by CC_PLL parameter // CLK180_DOUB - set by CC_PLL parameter
// CLK270_DOUB - set by CC_PLL parameter // CLK270_DOUB - set by CC_PLL parameter
// bits 6 and 7 are unused // bits 6 and 7 are unused
// TODO: USR_CLK_OUT - part of routing, mux from chipdb // USR_CLK_OUT - part of routing, mux from chipdb
if (ci.getPort(id_CLK0)) if (ci.getPort(id_CLK0))
ctx->addClock(ci.getPort(id_CLK0)->name, out_clk_max); ctx->addClock(ci.getPort(id_CLK0)->name, out_clk_max);