mirror of https://github.com/YosysHQ/nextpnr.git
frontend: don't connect a const net to ports connected to `x`. (#1447)
prjunnamed normalizes ports that are not present in the primitive to be all-x. On iCE40, this can cause a false placement conflict between `SB_IO` cells where one's clock input is `x` and another's is some other net.
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81ccada239
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@ -472,7 +472,10 @@ template <typename FrontendType> struct GenericFrontend
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ci->ports[port_bit_ids].type = dir;
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ci->ports[port_bit_ids].type = dir;
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// Resolve connectivity
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// Resolve connectivity
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NetInfo *net;
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NetInfo *net;
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if (impl.is_vector_bit_constant(bits, i)) {
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if (impl.is_vector_bit_undef(bits, i)) {
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// Don't connect it if it's an `x`
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continue;
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} else if (impl.is_vector_bit_constant(bits, i)) {
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// Create a constant driver if one is needed
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// Create a constant driver if one is needed
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net = create_constant_net(m, inst_name.str(ctx) + "." + port_bit_name + "$const",
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net = create_constant_net(m, inst_name.str(ctx) + "." + port_bit_name + "$const",
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impl.get_vector_bit_constval(bits, i));
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impl.get_vector_bit_constval(bits, i));
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@ -161,6 +161,12 @@ struct JsonFrontendImpl
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int get_vector_length(BitVectorDataType &bits) const { return int(bits.size()); }
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int get_vector_length(BitVectorDataType &bits) const { return int(bits.size()); }
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bool is_vector_bit_undef(BitVectorDataType &bits, int i) const
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{
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NPNR_ASSERT(i < int(bits.size()));
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return bits[i] == "x";
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}
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bool is_vector_bit_constant(BitVectorDataType &bits, int i) const
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bool is_vector_bit_constant(BitVectorDataType &bits, int i) const
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{
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{
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NPNR_ASSERT(i < int(bits.size()));
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NPNR_ASSERT(i < int(bits.size()));
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