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Merge 59c8f93a62 into 2fb1d1982f

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DavidClawson 2026-08-04 10:33:13 +02:00 committed by GitHub
parent 2fb1d1982f 59c8f93a62
commit acbb4ed71c
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2 changed files with 7 additions and 2 deletions
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2
himbaechel/uarch/gowin/CMakeLists.txt
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@ -25,7 +25,7 @@ add_nextpnr_himbaechel_microarchitecture(${uarch}
CORE_SOURCES ${SOURCES} CORE_SOURCES ${SOURCES}
) )
set(ALL_HIMBAECHEL_GOWIN_DEVICES GW1N-1 GW1NZ-1 GW1N-4 GW1N-9 GW1N-9C GW1NS-4 GW2A-18 GW2A-18C GW5A-25A GW5AST-138C) set(ALL_HIMBAECHEL_GOWIN_DEVICES GW1N-1 GW1N-2 GW1NZ-1 GW1N-4 GW1N-9 GW1N-9C GW1NS-4 GW2A-18 GW2A-18C GW5A-25A GW5AST-138C)
set(HIMBAECHEL_GOWIN_DEVICES ${ALL_HIMBAECHEL_GOWIN_DEVICES} CACHE STRING set(HIMBAECHEL_GOWIN_DEVICES ${ALL_HIMBAECHEL_GOWIN_DEVICES} CACHE STRING
"Include support for these Gowin devices (available: ${ALL_HIMBAECHEL_GOWIN_DEVICES})") "Include support for these Gowin devices (available: ${ALL_HIMBAECHEL_GOWIN_DEVICES})")
if (HIMBAECHEL_GOWIN_DEVICES STREQUAL "all") if (HIMBAECHEL_GOWIN_DEVICES STREQUAL "all")

7
himbaechel/uarch/gowin/gowin_arch_gen.py
View File

@ -1003,7 +1003,7 @@ def create_io_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int, tdesc:
tt = chip.create_tile_type(tiletype) tt = chip.create_tile_type(tiletype)
tt.extra_data = TileExtraData(chip.strs.id(typename)) tt.extra_data = TileExtraData(chip.strs.id(typename))
simple_io = y in db.simplio_rows and chip.name in {'GW1N-1', 'GW1NZ-1', 'GW1N-4'} simple_io = y in db.simplio_rows and chip.name in {'GW1N-1', 'GW1NZ-1', 'GW1N-2', 'GW1N-4'}
if simple_io: if simple_io:
rng = 10 rng = 10
else: else:
@ -1537,6 +1537,11 @@ def create_pll_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int, tdesc
else: else:
pll_name = 'RPLLA' pll_name = 'RPLLA'
bel_type = 'rPLL' bel_type = 'rPLL'
if pll_name not in db[y, x].bels:
# GW1N-2 (WIP): PLL not yet in chipdb (partType-1 extended table / M4).
# Emit the tile without a PLL bel so logic/routing/IO still round-trip.
tdesc.tiletype = tiletype
return tt
portmap = db[y, x].bels[pll_name].portmap portmap = db[y, x].bels[pll_name].portmap
pll = tt.create_bel("PLL", bel_type, z = PLL_Z) pll = tt.create_bel("PLL", bel_type, z = PLL_Z)
pll.flags = BEL_FLAG_GLOBAL pll.flags = BEL_FLAG_GLOBAL