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ice40: Fix accidental division by DIVR in 2_PAD mode 

Fixes #1500

Signed-off-by: gatecat <gatecat@ds0.me>
This commit is contained in:
gatecat 2025-06-25 11:43:22 +02:00
parent 0c86a218fd
commit a77eb9e941
1 changed files with 2 additions and 2 deletions
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4
ice40/pack.cc
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@ -1520,7 +1520,7 @@ void pack_plls(Context *ctx)
log_info(" Input frequency of PLL '%s' is constrained to %.1f MHz\n", ctx->nameOf(ci), log_info(" Input frequency of PLL '%s' is constrained to %.1f MHz\n", ctx->nameOf(ci),
MHz(ctx, input_constr)); MHz(ctx, input_constr));
// Input divider (DIVR) // Input divider (DIVR)
input_constr *= (int_or_default(packed->params, id_DIVR, 0) + 1); auto input_divr = input_constr * (int_or_default(packed->params, id_DIVR, 0) + 1);
delay_t vco_constr = 0; delay_t vco_constr = 0;
delay_t outa_constr = 0, outb_constr = 0; delay_t outa_constr = 0, outb_constr = 0;
int sr_div = 4; int sr_div = 4;
@ -1561,7 +1561,7 @@ void pack_plls(Context *ctx)
} }
} }
// Determine dividers in VCO path // Determine dividers in VCO path
vco_constr = input_constr / (int_or_default(packed->params, id_DIVF, 0) + 1); vco_constr = input_divr / (int_or_default(packed->params, id_DIVF, 0) + 1);
divq = 1 << (int_or_default(packed->params, id_DIVQ, 0)); divq = 1 << (int_or_default(packed->params, id_DIVQ, 0));
if (fbp_value != "1") // anything other than SIMPLE - feedback after DIVQ if (fbp_value != "1") // anything other than SIMPLE - feedback after DIVQ
vco_constr /= divq; vco_constr /= divq;