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Bit of cleanup

This commit is contained in:
Miodrag Milanovic 2025-07-03 10:24:53 +02:00
parent c0663d368d
commit 9d9f035c23
5 changed files with 29 additions and 40 deletions
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3
himbaechel/uarch/gatemate/bitstream.cc
View File

@ -264,8 +264,6 @@ struct BitstreamBackend
cc.tiles[loc].add_word(stringf("GPIO.%s", p.first.c_str(ctx)), p.second.as_bits());
}
break;
case id_CPE_LT_L.index:
case id_CPE_LT_U.index:
case id_CPE_CPLINES.index:
case id_CPE_COMP.index:
case id_CPE_L2T4.index:
@ -285,6 +283,7 @@ struct BitstreamBackend
// Update configuration bits based on signal inversion
dict<IdString, Property> params = cell.second->params;
Loc l = ctx->getBelLocation(cell.second->bel);
params.erase(id_L2T4_UPPER);
if (cell.second->type.in(id_CPE_L2T4, id_CPE_LT_L, id_CPE_LT_U)) {
if (l.z == CPE_LT_U_Z) {
update_cpe_lt(cell.second.get(), id_IN1, id_INIT_L00, params);

7
himbaechel/uarch/gatemate/cells.cc
View File

@ -39,11 +39,12 @@ CellInfo *GateMatePacker::create_cell_ptr(IdString type, IdString name)
add_port(id_IN3, PORT_IN);
add_port(id_IN4, PORT_IN);
add_port(id_OUT, PORT_OUT);
// These are used to propagate alternate inputs for first LUT2 levels
add_port(id_CINX, PORT_IN);
add_port(id_PINX, PORT_IN);
add_port(id_PINY1, PORT_IN);
if (type.in(id_CPE_LT_L, id_CPE_L2T5_L)) {
add_port(id_CINX, PORT_IN);
add_port(id_PINX, PORT_IN);
add_port(id_CINY1, PORT_IN);
add_port(id_PINY1, PORT_IN);
add_port(id_CINY2, PORT_IN);
add_port(id_PINY2, PORT_IN);

1
himbaechel/uarch/gatemate/constids.inc
View File

@ -2267,3 +2267,4 @@ X(CPE_CONCAT)
X(CPE_ADDCIN)
X(CPE_DUMMY)
X(CPE_LATCH)
X(L2T4_UPPER)

16
himbaechel/uarch/gatemate/gatemate.cc
View File

@ -195,25 +195,13 @@ void GateMateImpl::postPlace()
ctx->assignArchInfo();
std::vector<IdString> delete_cells;
for (auto &cell : ctx->cells) {
/// TODO: Remove this section when pack_mult is cleaned
if (cell.second->type.in(id_CPE_LT_L, id_CPE_LT_U) &&
int_or_default(cell.second->params, id_C_FUNCTION, 0) == 0) {
Loc l = ctx->getBelLocation(cell.second->bel);
if (l.z == CPE_LT_L_Z) {
if (!cell.second->params.count(id_INIT_L20))
cell.second->params[id_INIT_L20] = Property(0b1100, 4);
// Rename params since currently in pack_mult they have final names
// and we do rename again later for bitstream
rename_param(cell.second.get(), id_INIT_L02, id_INIT_L00, 4);
rename_param(cell.second.get(), id_INIT_L03, id_INIT_L01, 4);
rename_param(cell.second.get(), id_INIT_L11, id_INIT_L10, 4);
}
} else if (cell.second->type.in(id_CPE_L2T4)) {
if (cell.second->type.in(id_CPE_L2T4)) {
Loc l = ctx->getBelLocation(cell.second->bel);
if (l.z == CPE_LT_L_Z) {
if (!cell.second->params.count(id_INIT_L20))
cell.second->params[id_INIT_L20] = Property(0b1100, 4);
}
cell.second->params[id_L2T4_UPPER] = Property((l.z == CPE_LT_U_Z) ? 1 : 0, 1);
} else if (cell.second->type.in(id_CPE_L2T5_L, id_CPE_LT_L)) {
BelId bel = cell.second->bel;
PlaceStrength strength = cell.second->belStrength;

42
himbaechel/uarch/gatemate/pack_mult.cc
View File

@ -259,7 +259,7 @@ CarryGenCell::CarryGenCell(CellInfo *lower, CellInfo *upper, CellInfo *comp, Cel
cplines->params[id_C_SEL_C] = Property(1, 1); // COMP_OUT -> CY2_VAL
cplines->params[id_C_SELY2] = Property(0, 1); // COMP_OUT -> CY2_VAL
upper->params[id_C_O1] = Property(0b11, 2); // COMB1OUT -> OUT1
//upper->params[id_C_O1] = Property(0b11, 2); // COMB1OUT -> OUT1
}
MultfabCell::MultfabCell(CellInfo *lower, CellInfo *upper, CellInfo *comp, CellInfo *cplines, IdString name,
@ -269,7 +269,7 @@ MultfabCell::MultfabCell(CellInfo *lower, CellInfo *upper, CellInfo *comp, CellI
// TODO: perhaps C_I[1234] could be pips?
lower->params[id_INIT_L02] = Property(LUT_D1, 4); // PINY1
lower->params[id_INIT_L03] = Property(LUT_ZERO, 4); // (unused)
//lower->params[id_INIT_L03] = Property(LUT_ZERO, 4); // (unused)
lower->params[id_INIT_L11] = Property(LUT_D0, 4); // L02
lower->params[id_INIT_L20] = Property(is_even_x ? LUT_AND_INV_D0 : LUT_OR, 4); // L10 AND L11 -> OUT1
lower->params[id_C_FUNCTION] = Property(C_ADDCIN, 3);
@ -294,7 +294,7 @@ MultfabCell::MultfabCell(CellInfo *lower, CellInfo *upper, CellInfo *comp, CellI
cplines->params[id_C_SEL_P] = Property(0, 1); // OUT1 -> PY1_VAL
cplines->params[id_C_SELY1] = Property(0, 1); // COMP_OUT -> CY1_VAL; OUT1 -> PY1_VAL
upper->params[id_C_O1] = Property(0b11, 2); // COMB1OUT -> OUT1
//upper->params[id_C_O1] = Property(0b11, 2); // COMB1OUT -> OUT1
}
FRoutingCell::FRoutingCell(CellInfo *lower, CellInfo *upper, CellInfo *comp, CellInfo *cplines, IdString name,
@ -303,17 +303,17 @@ FRoutingCell::FRoutingCell(CellInfo *lower, CellInfo *upper, CellInfo *comp, Cel
{
// TODO: simplify AND with zero/OR with zero into something more sensical.
lower->params[id_INIT_L02] = Property(LUT_ZERO, 4); // (unused)
lower->params[id_INIT_L03] = Property(LUT_ONE, 4); // (unused)
lower->params[id_INIT_L11] = Property(LUT_AND, 4);
lower->params[id_INIT_L20] = Property(LUT_D1, 4);
//lower->params[id_INIT_L02] = Property(LUT_ZERO, 4); // (unused)
//lower->params[id_INIT_L03] = Property(LUT_ONE, 4); // (unused)
//lower->params[id_INIT_L11] = Property(LUT_AND, 4);
//lower->params[id_INIT_L20] = Property(LUT_D1, 4);
lower->params[id_C_FUNCTION] = Property(C_ADDCIN, 3);
comp->params[id_INIT_L30] = Property(is_even_x ? LUT_ONE : LUT_INV_D1, 4); // L10 -> COMP_OUT
upper->params[id_INIT_L00] = Property(LUT_D1, 4); // PINY1
upper->params[id_INIT_L01] = Property(LUT_ONE, 4); // (unused)
upper->params[id_INIT_L10] = Property(LUT_AND, 4);
//upper->params[id_INIT_L01] = Property(LUT_ONE, 4); // (unused)
upper->params[id_INIT_L10] = Property(LUT_D0, 4);
upper->params[id_C_I1] = Property(1, 1); // PINY1 for L00
upper->params[id_C_FUNCTION] = Property(C_ADDCIN, 3);
@ -326,8 +326,8 @@ FRoutingCell::FRoutingCell(CellInfo *lower, CellInfo *upper, CellInfo *comp, Cel
cplines->params[id_C_PY1_I] = Property(1, 1);
cplines->params[id_C_PY2_I] = Property(1, 1);
upper->params[id_C_O1] = Property(0b11, 2); // COMB1OUT -> OUT1
upper->params[id_C_O2] = Property(0b11, 2); // COMB2OUT -> OUT2
//upper->params[id_C_O1] = Property(0b11, 2); // COMB1OUT -> OUT1
//upper->params[id_C_O2] = Property(0b11, 2); // COMB2OUT -> OUT2
}
MultCell::MultCell(CellInfo *lower, CellInfo *upper, CellInfo *cplines, IdString name, bool is_msb)
@ -336,7 +336,7 @@ MultCell::MultCell(CellInfo *lower, CellInfo *upper, CellInfo *cplines, IdString
lower->params[id_INIT_L02] = Property(LUT_AND, 4);
lower->params[id_INIT_L03] = Property(LUT_D1, 4); // PINX
lower->params[id_INIT_L11] = Property(LUT_XOR, 4);
lower->params[id_INIT_L20] = Property(LUT_D1, 4); // L11
//lower->params[id_INIT_L20] = Property(LUT_D1, 4); // L11
lower->params[id_C_FUNCTION] = Property(C_MULT, 3);
upper->params[id_INIT_L00] = Property(LUT_AND, 4);
@ -351,10 +351,10 @@ MultCell::MultCell(CellInfo *lower, CellInfo *upper, CellInfo *cplines, IdString
if (is_msb) {
cplines->params[id_C_PY1_I] = Property(1, 1);
cplines->params[id_C_C_P] = Property(1, 1); // TODO: check with Micko
lower->params[id_C_C_P] = Property(1, 1);
} else {
cplines->params[id_C_PY1_I] = Property(0, 1);
cplines->params[id_C_C_P] = Property(0, 1); // TODO: check with Micko
lower->params[id_C_C_P] = Property(0, 1);
}
upper->params[id_C_O1] = Property(0b10, 2); // CP_OUT1 -> OUT1
@ -364,10 +364,10 @@ MultCell::MultCell(CellInfo *lower, CellInfo *upper, CellInfo *cplines, IdString
MsbRoutingCell::MsbRoutingCell(CellInfo *lower, CellInfo *upper, CellInfo *comp, CellInfo *cplines, IdString name)
: lower{lower}, upper{upper}, comp{comp}, cplines{cplines}
{
lower->params[id_INIT_L02] = Property(LUT_ZERO, 4); // (unused)
lower->params[id_INIT_L03] = Property(LUT_ZERO, 4); // (unused)
lower->params[id_INIT_L11] = Property(LUT_ZERO, 4); // (unused)
lower->params[id_INIT_L20] = Property(LUT_ZERO, 4); // (unused)
//lower->params[id_INIT_L02] = Property(LUT_ZERO, 4); // (unused)
//lower->params[id_INIT_L03] = Property(LUT_ZERO, 4); // (unused)
//lower->params[id_INIT_L11] = Property(LUT_ZERO, 4); // (unused)
//lower->params[id_INIT_L20] = Property(LUT_ZERO, 4); // (unused)
comp->params[id_INIT_L30] = Property(LUT_ONE, 4); // zero -> COMP_OUT (L30 is inverted)
@ -503,8 +503,8 @@ void GateMatePacker::pack_mult()
}
{
auto *msb_route_lower = create_cell_ptr(id_CPE_LT_L, ctx->idf("%s$msb_route_lower", name.c_str(ctx)));
auto *msb_route_upper = create_cell_ptr(id_CPE_LT_U, ctx->idf("%s$msb_route_upper", name.c_str(ctx)));
auto *msb_route_lower = create_cell_ptr(id_CPE_DUMMY, ctx->idf("%s$msb_route_lower", name.c_str(ctx)));
auto *msb_route_upper = create_cell_ptr(id_CPE_L2T4, ctx->idf("%s$msb_route", name.c_str(ctx)));
auto *msb_route_comp = create_cell_ptr(id_CPE_COMP, ctx->idf("%s$msb_route_comp", name.c_str(ctx)));
auto *msb_route_lines = create_cell_ptr(id_CPE_CPLINES, ctx->idf("%s$msb_route_lines", name.c_str(ctx)));
@ -871,7 +871,7 @@ void GateMatePacker::pack_mult()
ctx->createNet(ctx->idf("%s$%s$b%d", lines_name.c_str(ctx), lower_net_name.c_str(ctx), 2 * b));
b_mult.cplines->connectPort(id_POUTY1, lower_net);
b_msb_route.cplines->connectPort(id_PINY1, lower_net);
b_msb_route.lower->connectPort(id_PINY1, lower_net); // TODO: verify this with Micko
b_msb_route.upper->connectPort(id_PINY1, lower_net);
auto *upper_net = ctx->createNet(
ctx->idf("%s$%s$b%d", lines_name.c_str(ctx), lower_net_name.c_str(ctx), 2 * b + 1));