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Merge 053a6d5cdb into 7bd1336f88

This commit is contained in:
Miodrag Milanović 2025-12-24 12:12:47 +00:00 committed by GitHub
parent 7bd1336f88 053a6d5cdb
commit 989d776533
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GPG Key ID: B5690EEEBB952194
3 changed files with 44 additions and 6 deletions
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12
himbaechel/uarch/gatemate/constids.inc
View File

@ -925,6 +925,10 @@ X(CINX)
X(CPE_FF_U)
// CPE_FF_U pins
X(DIN)
X(CLK_INT)
X(EN_INT)
X(CINY2)
X(PINY2)
//X(CLK)
//X(EN)
//X(SR)
@ -958,8 +962,8 @@ X(COMBIN)
X(PINX)
X(CINY1)
//X(PINY1)
X(CINY2)
X(PINY2)
//X(CINY2)
//X(PINY2)
X(COUTX)
X(POUTX)
X(COUTY1)
@ -971,6 +975,10 @@ X(POUTY2)
X(CPE_FF_L)
// CPE_FF_L pins
//X(DIN)
//X(CLK_INT)
//X(EN_INT)
//X(CINY2)
//X(PINY2)
//X(CLK)
//X(EN)
//X(SR)

26
himbaechel/uarch/gatemate/gatemate.cc
View File

@ -454,11 +454,15 @@ void GateMateImpl::postRoute()
{ctx->id("CPE.IN1"), id_IN1}, {ctx->id("CPE.IN2"), id_IN2}, {ctx->id("CPE.IN3"), id_IN3},
{ctx->id("CPE.IN4"), id_IN4}, {ctx->id("CPE.IN5"), id_IN1}, {ctx->id("CPE.IN6"), id_IN2},
{ctx->id("CPE.IN7"), id_IN3}, {ctx->id("CPE.IN8"), id_IN4}, {ctx->id("CPE.PINY1"), id_PINY1},
{ctx->id("CPE.PINY2"), id_PINY2}, {ctx->id("CPE.CINY2"), id_CINY2},
{ctx->id("CPE.CLK"), id_CLK}, {ctx->id("CPE.EN"), id_EN},
{ctx->id("CPE.CINX"), id_CINX}, {ctx->id("CPE.PINX"), id_PINX}};
static dict<IdString, IdString> convert_port_merged = {
{ctx->id("CPE.IN1"), id_IN1}, {ctx->id("CPE.IN2"), id_IN2}, {ctx->id("CPE.IN3"), id_IN3},
{ctx->id("CPE.IN4"), id_IN4}, {ctx->id("CPE.IN5"), id_IN5}, {ctx->id("CPE.IN6"), id_IN6},
{ctx->id("CPE.IN7"), id_IN7}, {ctx->id("CPE.IN8"), id_IN8}, {ctx->id("CPE.PINY1"), id_PINY1},
{ctx->id("CPE.PINY2"), id_PINY2}, {ctx->id("CPE.CINY2"), id_CINY2},
{ctx->id("CPE.CLK"), id_CLK}, {ctx->id("CPE.EN"), id_EN},
{ctx->id("CPE.CINX"), id_CINX}, {ctx->id("CPE.PINX"), id_PINX}};
if (convert_port.count(port)) {
port_mapping.emplace(orig_port, merged ? convert_port_merged[port] : convert_port[port]);
@ -641,6 +645,24 @@ void GateMateImpl::postRoute()
if (cfg.count(id_C_I4) && cfg.at(id_C_I4) == 1)
cell.second->params[id_C_I4] = Property(1, 1);
}
if (cell.second->type.in(id_CPE_FF, id_CPE_FF_L, id_CPE_FF_U, id_CPE_LATCH)) {
cfg.clear();
port_mapping.clear();
check_input(cell.second.get(), id_CLK_INT, false);
check_input(cell.second.get(), id_EN_INT, false);
if (cfg.count(id_C_CLKSEL) && cfg.at(id_C_CLKSEL) == 1) {
uint8_t val = int_or_default(cell.second->params, id_C_CPE_CLK, 0) & 1;
cell.second->params[id_C_CPE_CLK] = Property(val ? 3 : 0, 2);
cell.second->params[id_C_CLKSEL] = Property(1, 1);
}
if (cfg.count(id_C_ENSEL) && cfg.at(id_C_ENSEL) == 1) {
uint8_t val = int_or_default(cell.second->params, id_C_CPE_EN, 0) & 1;
cell.second->params[id_C_CPE_EN] = Property(val ? 3 : 0, 2);
cell.second->params[id_C_ENSEL] = Property(1, 1);
}
cell.second->renamePort(id_CLK_INT, port_mapping[id_CLK_INT]);
cell.second->renamePort(id_EN_INT, port_mapping[id_EN_INT]);
}
}
ctx->assignArchInfo();
@ -718,8 +740,8 @@ void GateMateImpl::assign_cell_info()
CellInfo *ci = cell.second.get();
auto &fc = fast_cell_info.at(ci->flat_index);
if (getBelBucketForCellType(ci->type) == id_CPE_FF) {
fc.ff_en = ci->getPort(id_EN);
fc.ff_clk = ci->getPort(id_CLK);
fc.ff_en = ci->getPort(id_EN_INT);
fc.ff_clk = ci->getPort(id_CLK_INT);
fc.ff_sr = ci->getPort(id_SR);
fc.config = get_dff_config(ci);
fc.used = true;

12
himbaechel/uarch/gatemate/pack_cpe.cc
View File

@ -33,9 +33,9 @@ bool GateMatePacker::are_ffs_compatible(CellInfo *dff, CellInfo *other)
{
if (!other)
return true;
if (dff->getPort(id_CLK) != other->getPort(id_CLK))
if (dff->getPort(id_CLK_INT) != other->getPort(id_CLK))
return false;
if (dff->getPort(id_EN) != other->getPort(id_EN))
if (dff->getPort(id_EN_INT) != other->getPort(id_EN))
return false;
if (dff->getPort(id_SR) != other->getPort(id_SR))
return false;
@ -192,6 +192,8 @@ void GateMatePacker::pack_cpe()
ci.constr_children.push_back(dff);
dff->renamePort(id_D, id_DIN);
dff->renamePort(id_Q, id_DOUT);
dff->renamePort(id_CLK, id_CLK_INT);
dff->renamePort(id_EN, id_EN_INT);
dff->type = (dff->type == id_CC_DLT) ? id_CPE_LATCH : id_CPE_FF;
};
@ -387,6 +389,8 @@ void GateMatePacker::pack_cpe()
ci.cluster = ci.name;
ci.constr_children.push_back(lt);
ci.renamePort(id_Q, id_DOUT);
ci.renamePort(id_CLK, id_CLK_INT);
ci.renamePort(id_EN, id_EN_INT);
NetInfo *d_net = ci.getPort(id_D);
if (d_net == net_PACKER_GND) {
lt->params[id_INIT_L10] = Property(LUT_ZERO, 4);
@ -537,6 +541,8 @@ void GateMatePacker::pack_addf()
cell->constr_children.push_back(dff);
dff->renamePort(id_D, id_DIN);
dff->renamePort(id_Q, id_DOUT);
dff->renamePort(id_CLK, id_CLK_INT);
dff->renamePort(id_EN, id_EN_INT);
dff->type = (dff->type == id_CC_DLT) ? id_CPE_LATCH : id_CPE_FF;
return dff;
}
@ -763,6 +769,8 @@ std::pair<CellInfo *, CellInfo *> GateMatePacker::move_ram_io(CellInfo *cell, Id
/* if (ci.type.in(id_CC_DFF, id_CC_DLT)) {
cpe_half = create_cell_ptr(id_CPE_L2T4, ctx->idf("%s$%s_cpe", cell->name.c_str(ctx), oPort.c_str(ctx)));
ci.renamePort(id_Q, id_DOUT);
ci.renamePort(id_CLK, id_CLK_INT);
ci.renamePort(id_EN, id_EN_INT);
NetInfo *d_net = ci.getPort(id_D);
if (d_net == net_PACKER_GND) {
cpe_half->params[id_INIT_L10] = Property(LUT_ZERO, 4);