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xilinx: Stub predictDelay implementation 

Signed-off-by: gatecat <gatecat@ds0.me>
This commit is contained in:
gatecat 2026-03-04 11:28:10 +01:00
parent f177c39c0b
commit 8c40db213a
2 changed files with 10 additions and 0 deletions
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9
himbaechel/uarch/xilinx/xilinx.cc
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@ -647,6 +647,15 @@ delay_t XilinxImpl::estimateDelay(WireId src, WireId dst) const
return 800 + 50 * (std::abs(dy - sy) + std::abs(dx - sx)); return 800 + 50 * (std::abs(dy - sy) + std::abs(dx - sx));
} }
delay_t XilinxImpl::predictDelay(BelId src_bel, IdString src_pin, BelId dst_bel, IdString dst_pin) const
{
int sx, sy, dx, dy;
tile_xy(ctx->chip_info, src_bel.tile, sx, sy);
tile_xy(ctx->chip_info, dst_bel.tile, dx, dy);
// TODO: improve sophistication here based on old nextpnr-xilinx code
return 500 + 50 * (std::abs(dy - sy) + std::abs(dx - sx));
}
BoundingBox XilinxImpl::getRouteBoundingBox(WireId src, WireId dst) const BoundingBox XilinxImpl::getRouteBoundingBox(WireId src, WireId dst) const
{ {
int x0, y0, x1, y1; int x0, y0, x1, y1;

1
himbaechel/uarch/xilinx/xilinx.h
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@ -175,6 +175,7 @@ struct XilinxImpl : HimbaechelAPI
bool is_general_routing(WireId wire) const; bool is_general_routing(WireId wire) const;
void find_source_sink_locs(); void find_source_sink_locs();
delay_t predictDelay(BelId src_bel, IdString src_pin, BelId dst_bel, IdString dst_pin) const override;
delay_t estimateDelay(WireId src, WireId dst) const override; delay_t estimateDelay(WireId src, WireId dst) const override;
BoundingBox getRouteBoundingBox(WireId src, WireId dst) const override; BoundingBox getRouteBoundingBox(WireId src, WireId dst) const override;