mirror of https://github.com/YosysHQ/nextpnr.git
gatemate/pack_bram: handle dynamic almost full/empty offsets
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09db7c3fb7
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@ -361,7 +361,7 @@ void GateMatePacker::pack_ram()
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log_error("The FIFO configuration of A_WIDTH and B_WIDTH must be equal.\n");
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if (a_rd_width != 80 && ram_mode == 1)
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log_error("FIFO SDP is ony supported in 80 bit mode.\n");
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log_error("FIFO SDP is only supported in 80 bit mode.\n");
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ci.params[id_RAM_cfg_input_config_b0] = Property(width_to_config(b_wr_width), 3);
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ci.params[id_RAM_cfg_output_config_a0] = Property(width_to_config(a_rd_width), 3);
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@ -377,19 +377,27 @@ void GateMatePacker::pack_ram()
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else
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ci.params[id_RAM_cfg_fifo_async_enable] = Property(0b1, 1);
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// TODO: Handle dynamic almost empty/full
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int dyn_stat_select = int_or_default(ci.params, id_DYN_STAT_SELECT, 0);
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if (dyn_stat_select != 0 && dyn_stat_select != 1)
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log_error("DYN_STAT_SELECT must be 0 or 1.\n");
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if (dyn_stat_select != 0 && ram_mode == 1)
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log_error("Dynamic FIFO offset configuration is not supported in SDP mode.\n");
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if (dyn_stat_select != 0)
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log_error("Dynamic FIFO offset configuration is currently not supported.\n");
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ci.params[id_RAM_cfg_dyn_stat_select] = Property(dyn_stat_select << 1, 2);
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ci.params[id_RAM_cfg_almost_empty_offset] =
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Property(int_or_default(ci.params, id_ALMOST_EMPTY_OFFSET, 0), 15);
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ci.params[id_RAM_cfg_almost_full_offset] =
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Property(int_or_default(ci.params, id_ALMOST_FULL_OFFSET, 0), 15);
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if (dyn_stat_select != 0 && ram_mode == 0) {
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for (int i = 0; i < 15; ++i) {
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// WEA[14:0] = F_ALMOST_EMPTY_OFFSET
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ci.disconnectPort(ctx->idf("WEA[%d]", i));
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ci.renamePort(ctx->idf("F_ALMOST_EMPTY_OFFSET[%d]", i), ctx->idf("WEA[%d]", i));
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// WEA[34:20] = F_ALMOST_FULL_OFFSET
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ci.disconnectPort(ctx->idf("WEA[%d]", 20 + i));
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ci.renamePort(ctx->idf("F_ALMOST_FULL_OFFSET[%d]", i), ctx->idf("WEA[%d]", 20 + i));
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}
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}
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}
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for (int i = 0; i < 40; i++) {
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