luke
/
nextpnr
mirror of https://github.com/YosysHQ/nextpnr.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

gatemate: use BUFG input in case it is routed to PLL

This commit is contained in:
Miodrag Milanovic 2025-05-20 09:30:27 +02:00
parent 520616248e
commit 77a6df131c
1 changed files with 6 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
himbaechel/uarch/gatemate/pack_clocking.cc
View File

@ -259,6 +259,12 @@ void GateMatePacker::pack_pll()
NetInfo *clk = ci.getPort(id_CLK_REF); NetInfo *clk = ci.getPort(id_CLK_REF);
delay_t period = ctx->getDelayFromNS(1.0e9 / ctx->setting<float>("target_freq")); delay_t period = ctx->getDelayFromNS(1.0e9 / ctx->setting<float>("target_freq"));
if (clk) { if (clk) {
if (ctx->getBelBucketForCellType(clk->driver.cell->type) == id_CC_BUFG) {
NetInfo *in = clk->driver.cell->getPort(id_I);
ci.disconnectPort(id_CLK_REF);
ci.connectPort(id_CLK_REF, in);
clk = in;
}
if (ctx->getBelBucketForCellType(clk->driver.cell->type) != id_GPIO) if (ctx->getBelBucketForCellType(clk->driver.cell->type) != id_GPIO)
log_error("CLK_REF must be driven with GPIO pin.\n"); log_error("CLK_REF must be driven with GPIO pin.\n");
auto pad_info = uarch->bel_to_pad[clk->driver.cell->bel]; auto pad_info = uarch->bel_to_pad[clk->driver.cell->bel];