luke
/
nextpnr
mirror of https://github.com/YosysHQ/nextpnr.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

kernel: look up ports when applying clock constraints. (#1448) 

prjunnamed does not emit a net alias for toplevel ports. This works
fine for constraining IOs but breaks clock constraints. This commit
expands clock constraint application code to look up net aliases first,
ports second.
This commit is contained in:
Catherine 2025-01-31 08:30:39 +00:00 committed by GitHub
parent b64bf018ea
commit 77187613e3
No known key found for this signature in database
GPG Key ID: B5690EEEBB952194
1 changed files with 7 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
common/kernel/basectx.cc
View File

@ -100,12 +100,15 @@ void BaseCtx::addClock(IdString net, float freq)
cc->period = DelayPair(getCtx()->getDelayFromNS(1000 / freq));
cc->high = DelayPair(getCtx()->getDelayFromNS(500 / freq));
cc->low = DelayPair(getCtx()->getDelayFromNS(500 / freq));
if (!net_aliases.count(net)) {
log_warning("net '%s' does not exist in design, ignoring clock constraint\n", net.c_str(this));
} else {
if (net_aliases.count(net)) {
getNetByAlias(net)->clkconstr = std::move(cc);
log_info("constraining clock net '%s' to %.02f MHz\n", net.c_str(this), freq);
} else if (ports.count(net)) {
ports[net].net->clkconstr = std::move(cc);
} else {
log_warning("net '%s' does not exist in design, ignoring clock constraint\n", net.c_str(this));
return;
}
log_info("constraining clock net '%s' to %.02f MHz\n", net.c_str(this), freq);
}
void BaseCtx::createRectangularRegion(IdString name, int x0, int y0, int x1, int y1)