mirror of https://github.com/YosysHQ/nextpnr.git
Make sure we at least generate bitstream with all info
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1404954a26
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6dc5d8c98a
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@ -284,7 +284,7 @@ struct BitstreamBackend
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// Update configuration bits based on signal inversion
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dict<IdString, Property> params = cell.second->params;
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Loc l = ctx->getBelLocation(cell.second->bel);
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if (cell.second->type.in(id_CPE_L2T4, id_CPE_CI)) {
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if (cell.second->type.in(id_CPE_L2T4, id_CPE_CI, id_CPE_LT_L, id_CPE_LT_U)) {
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if (l.z == CPE_LT_U_Z) {
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update_cpe_lt(cell.second.get(), id_IN1, id_INIT_L00, params);
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update_cpe_lt(cell.second.get(), id_IN2, id_INIT_L00, params);
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@ -195,7 +195,19 @@ void GateMateImpl::postPlace()
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ctx->assignArchInfo();
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std::vector<IdString> delete_cells;
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for (auto &cell : ctx->cells) {
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if (cell.second->type.in(id_CPE_L2T4, id_CPE_CI)) {
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/// TODO: Remove this section when pack_mult is cleaned
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if (cell.second->type.in(id_CPE_LT_L,id_CPE_LT_U) && int_or_default(cell.second->params, id_C_FUNCTION, 0)==0) {
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Loc l = ctx->getBelLocation(cell.second->bel);
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if (l.z == CPE_LT_L_Z) {
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if (!cell.second->params.count(id_INIT_L20))
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cell.second->params[id_INIT_L20] = Property(0b1100, 4);
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// Rename params since currently in pack_mult they have final names
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// and we do rename again later for bitstream
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rename_param(cell.second.get(), id_INIT_L02, id_INIT_L00, 4);
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rename_param(cell.second.get(), id_INIT_L03, id_INIT_L01, 4);
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rename_param(cell.second.get(), id_INIT_L11, id_INIT_L10, 4);
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}
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} else if (cell.second->type.in(id_CPE_L2T4, id_CPE_CI)) {
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Loc l = ctx->getBelLocation(cell.second->bel);
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if (l.z == CPE_LT_L_Z) {
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if (!cell.second->params.count(id_INIT_L20))
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