ice40: Testing the placement validity check

Signed-off-by: David Shah <[email protected]>
This commit is contained in:
David Shah
2018-06-12 14:39:49 +02:00
parent 95fb0595a5
commit 5a9ff4aea1
2 changed files with 28 additions and 1 deletions
+1 -1
View File
@@ -12,4 +12,4 @@ yosys -p "rename chip gate;\
proc;\
clk2fflogic;\
miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp gold gate miter;\
sat -dump_vcd equiv_${NAME}.vcd -verify-no-timeout -timeout 20 -seq 10 -prove trigger 0 -prove-skip 1 -show-inputs -show-outputs miter" ${NAME}_out.v
sat -dump_vcd equiv_${NAME}.vcd -verify-no-timeout -timeout 60 -seq 50 -prove trigger 0 -prove-skip 1 -show-inputs -show-outputs miter" ${NAME}_out.v