mirror of https://github.com/YosysHQ/nextpnr.git
ecp5: Fix timing for DCU clock outputs
Signed-off-by: gatecat <gatecat@ds0.me>
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e6ecd8fab4
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4e9debe4e5
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@ -1015,6 +1015,8 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, in
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} else if (cell->type.in(id_DCUA, id_EXTREFB, id_PCSCLKDIV)) {
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} else if (cell->type.in(id_DCUA, id_EXTREFB, id_PCSCLKDIV)) {
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if (port.in(id_CH0_FF_TXI_CLK, id_CH0_FF_RXI_CLK, id_CH1_FF_TXI_CLK, id_CH1_FF_RXI_CLK))
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if (port.in(id_CH0_FF_TXI_CLK, id_CH0_FF_RXI_CLK, id_CH1_FF_TXI_CLK, id_CH1_FF_RXI_CLK))
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return TMG_CLOCK_INPUT;
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return TMG_CLOCK_INPUT;
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if (port.in(id_CH0_FF_TX_PCLK, id_CH0_FF_RX_PCLK, id_CH1_FF_TX_PCLK, id_CH1_FF_RX_PCLK))
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return TMG_GEN_CLOCK;
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std::string prefix = port.str(this).substr(0, 9);
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std::string prefix = port.str(this).substr(0, 9);
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if (prefix == "CH0_FF_TX" || prefix == "CH0_FF_RX" || prefix == "CH1_FF_TX" || prefix == "CH1_FF_RX") {
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if (prefix == "CH0_FF_TX" || prefix == "CH0_FF_RX" || prefix == "CH1_FF_TX" || prefix == "CH1_FF_RX") {
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clockInfoCount = 1;
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clockInfoCount = 1;
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