mirror of https://github.com/YosysHQ/nextpnr.git
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This commit is contained in:
Miodrag Milanovic
parent
1c9c7ff39e
commit
37f4e39ab5
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@ -72,31 +72,39 @@ struct BPassThroughCell
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// TODO: Micko points out this is an L2T4 CPE_HALF
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struct CarryGenCell
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{
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CarryGenCell() : lower{nullptr}, upper{nullptr} {}
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CarryGenCell(CellInfo *lower, CellInfo *upper, IdString name, bool is_odd_x, bool enable_cinx);
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CarryGenCell() : lower{nullptr}, upper{nullptr}, comp{nullptr}, cplines{nullptr} {}
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CarryGenCell(CellInfo *lower, CellInfo *upper, CellInfo *comp, CellInfo *cplines, IdString name, bool is_odd_x,
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bool enable_cinx);
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CellInfo *lower;
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CellInfo *upper;
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CellInfo *comp;
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CellInfo *cplines;
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};
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// This prepares B bits for multiplication.
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struct MultfabCell
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{
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MultfabCell() : lower{nullptr}, upper{nullptr} {}
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MultfabCell(CellInfo *lower, CellInfo *upper, IdString name, bool is_even_x, bool enable_cinx);
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MultfabCell() : lower{nullptr}, upper{nullptr}, comp{nullptr}, cplines{nullptr} {}
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MultfabCell(CellInfo *lower, CellInfo *upper, CellInfo *comp, CellInfo *cplines, IdString name, bool is_even_x,
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bool enable_cinx);
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CellInfo *lower;
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CellInfo *upper;
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CellInfo *comp;
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CellInfo *cplines;
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};
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// CITE: CPE_ges_f-routing-1.pdf
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struct FRoutingCell
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{
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FRoutingCell() : lower{nullptr}, upper{nullptr} {}
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FRoutingCell(CellInfo *lower, CellInfo *upper, IdString name, bool is_even_x);
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FRoutingCell() : lower{nullptr}, upper{nullptr}, comp{nullptr}, cplines{nullptr} {}
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FRoutingCell(CellInfo *lower, CellInfo *upper, CellInfo *comp, CellInfo *cplines, IdString name, bool is_even_x);
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CellInfo *lower;
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CellInfo *upper;
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CellInfo *comp;
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CellInfo *cplines;
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};
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// Multiply two bits of A with two bits of B.
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@ -114,11 +122,13 @@ struct MultCell
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// CITE: CPE_ges_MSB-routing.pdf
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struct MsbRoutingCell
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{
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MsbRoutingCell() : lower{nullptr}, upper{nullptr} {}
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MsbRoutingCell(CellInfo *lower, CellInfo *upper, IdString name);
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MsbRoutingCell() : lower{nullptr}, upper{nullptr}, comp{nullptr}, cplines{nullptr} {}
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MsbRoutingCell(CellInfo *lower, CellInfo *upper, CellInfo *comp, CellInfo *cplines, IdString name);
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CellInfo *lower;
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CellInfo *upper;
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CellInfo *comp;
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CellInfo *cplines;
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};
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struct MultiplierColumn
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@ -190,7 +200,8 @@ void APassThroughCell::clean_up_cell(Context *ctx, CellInfo *cell)
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}
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// B0 -> POUTY1; B1 -> COUTY1
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BPassThroughCell::BPassThroughCell(CellInfo *lower, CellInfo *upper, CellInfo *cplines, IdString name) : lower{lower}, upper{upper}, cplines(cplines)
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BPassThroughCell::BPassThroughCell(CellInfo *lower, CellInfo *upper, CellInfo *cplines, IdString name)
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: lower{lower}, upper{upper}, cplines(cplines)
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{
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lower->params[id_INIT_L00] = Property(LUT_D0, 4); // IN5
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lower->params[id_INIT_L01] = Property(LUT_ZERO, 4); // (unused)
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@ -222,34 +233,37 @@ void BPassThroughCell::clean_up_cell(Context *ctx, CellInfo *cell)
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}
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}
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CarryGenCell::CarryGenCell(CellInfo *lower, CellInfo *upper, IdString name, bool is_odd_x, bool enable_cinx)
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: lower{lower}, upper{upper}
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CarryGenCell::CarryGenCell(CellInfo *lower, CellInfo *upper, CellInfo *comp, CellInfo *cplines, IdString name,
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bool is_odd_x, bool enable_cinx)
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: lower{lower}, upper{upper}, comp{comp}, cplines{cplines}
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{
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lower->params[id_INIT_L02] = Property(LUT_D1, 4); // PINY1
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lower->params[id_INIT_L03] = Property(LUT_ZERO, 4); // (overriden by CIN)
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lower->params[id_INIT_L11] = Property(is_odd_x ? LUT_OR : LUT_ZERO, 4);
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lower->params[id_INIT_L20] = Property(is_odd_x ? LUT_OR : LUT_ZERO, 4);
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lower->params[id_INIT_L30] = Property(LUT_INV_D0, 4); // OUT1 -> COMP_OUT
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lower->params[id_C_FUNCTION] = Property(C_EN_CIN, 3);
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comp->params[id_INIT_L30] = Property(LUT_INV_D0, 4); // OUT1 -> COMP_OUT
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upper->params[id_INIT_L00] = Property(LUT_ZERO, 4); // (unused)
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upper->params[id_INIT_L01] = Property(enable_cinx ? LUT_D1 : LUT_ZERO, 4); // CINX
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upper->params[id_INIT_L10] = Property(LUT_D1, 4);
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upper->params[id_C_I2] = Property(1, 1); // CINX for L01
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upper->params[id_C_I3] = Property(1, 1); // PINY1 for L02
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upper->params[id_C_FUNCTION] = Property(C_EN_CIN, 3);
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upper->params[id_C_PY1_I] = Property(0, 1); // PINY1 -> POUTY1
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upper->params[id_C_CY1_I] = Property(0, 1); // CINY1 -> COUTY1
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upper->params[id_C_CY2_I] = Property(1, 1); // CY2_VAL -> COUTY2
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upper->params[id_C_SEL_C] = Property(1, 1); // COMP_OUT -> CY2_VAL
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upper->params[id_C_SELY2] = Property(0, 1); // COMP_OUT -> CY2_VAL
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cplines->params[id_C_PY1_I] = Property(0, 1); // PINY1 -> POUTY1
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cplines->params[id_C_CY1_I] = Property(0, 1); // CINY1 -> COUTY1
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cplines->params[id_C_CY2_I] = Property(1, 1); // CY2_VAL -> COUTY2
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cplines->params[id_C_SEL_C] = Property(1, 1); // COMP_OUT -> CY2_VAL
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cplines->params[id_C_SELY2] = Property(0, 1); // COMP_OUT -> CY2_VAL
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upper->params[id_C_O1] = Property(0b11, 2); // COMB1OUT -> OUT1
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}
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MultfabCell::MultfabCell(CellInfo *lower, CellInfo *upper, IdString name, bool is_even_x, bool enable_cinx)
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: lower{lower}, upper{upper}
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MultfabCell::MultfabCell(CellInfo *lower, CellInfo *upper, CellInfo *comp, CellInfo *cplines, IdString name,
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bool is_even_x, bool enable_cinx)
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: lower{lower}, upper{upper}, comp{comp}, cplines{cplines}
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{
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// TODO: perhaps C_I[1234] could be pips?
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@ -257,9 +271,10 @@ MultfabCell::MultfabCell(CellInfo *lower, CellInfo *upper, IdString name, bool i
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lower->params[id_INIT_L03] = Property(LUT_ZERO, 4); // (unused)
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lower->params[id_INIT_L11] = Property(LUT_D0, 4); // L02
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lower->params[id_INIT_L20] = Property(is_even_x ? LUT_AND_INV_D0 : LUT_OR, 4); // L10 AND L11 -> OUT1
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lower->params[id_INIT_L30] = Property(LUT_INV_D1, 4); // L10 -> COMP_OUT
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lower->params[id_C_FUNCTION] = Property(C_ADDCIN, 3);
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comp->params[id_INIT_L30] = Property(LUT_INV_D1, 4); // L10 -> COMP_OUT
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upper->params[id_INIT_L00] = Property(LUT_D1, 4); // PINY1
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upper->params[id_INIT_L01] = Property(enable_cinx ? LUT_D1 : LUT_ZERO, 4); // CINX
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upper->params[id_INIT_L10] = Property(LUT_XOR, 4); // XOR
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@ -268,19 +283,22 @@ MultfabCell::MultfabCell(CellInfo *lower, CellInfo *upper, IdString name, bool i
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upper->params[id_C_I2] = Property(1, 1); // CINX for L01
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upper->params[id_C_I3] = Property(1, 1); // PINY1 for L02
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upper->params[id_C_FUNCTION] = Property(C_ADDCIN, 3);
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upper->params[id_C_SELX] = Property(1, 1); // inverted CINY2 -> CX_VAL
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upper->params[id_C_SEL_C] = Property(1, 1); // inverted CINY2 -> CX_VAL; COMP_OUT -> CY1_VAL
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upper->params[id_C_Y12] = Property(1, 1); // inverted CINY2 -> CX_VAL
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upper->params[id_C_CX_I] = Property(1, 1); // CX_VAL -> COUTX
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upper->params[id_C_CY1_I] = Property(1, 1); // CY1_VAL -> COUTY1
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upper->params[id_C_PY1_I] = Property(1, 1); // PY1_VAL -> POUTY1
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upper->params[id_C_SEL_P] = Property(0, 1); // OUT1 -> PY1_VAL
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upper->params[id_C_SELY1] = Property(0, 1); // COMP_OUT -> CY1_VAL; OUT1 -> PY1_VAL
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cplines->params[id_C_SELX] = Property(1, 1); // inverted CINY2 -> CX_VAL
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cplines->params[id_C_SEL_C] = Property(1, 1); // inverted CINY2 -> CX_VAL; COMP_OUT -> CY1_VAL
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cplines->params[id_C_Y12] = Property(1, 1); // inverted CINY2 -> CX_VAL
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cplines->params[id_C_CX_I] = Property(1, 1); // CX_VAL -> COUTX
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cplines->params[id_C_CY1_I] = Property(1, 1); // CY1_VAL -> COUTY1
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cplines->params[id_C_PY1_I] = Property(1, 1); // PY1_VAL -> POUTY1
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cplines->params[id_C_SEL_P] = Property(0, 1); // OUT1 -> PY1_VAL
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cplines->params[id_C_SELY1] = Property(0, 1); // COMP_OUT -> CY1_VAL; OUT1 -> PY1_VAL
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upper->params[id_C_O1] = Property(0b11, 2); // COMB1OUT -> OUT1
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}
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FRoutingCell::FRoutingCell(CellInfo *lower, CellInfo *upper, IdString name, bool is_even_x) : lower{lower}, upper{upper}
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FRoutingCell::FRoutingCell(CellInfo *lower, CellInfo *upper, CellInfo *comp, CellInfo *cplines, IdString name,
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bool is_even_x)
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: lower{lower}, upper{upper}, comp{comp}, cplines{cplines}
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{
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// TODO: simplify AND with zero/OR with zero into something more sensical.
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@ -288,23 +306,24 @@ FRoutingCell::FRoutingCell(CellInfo *lower, CellInfo *upper, IdString name, bool
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lower->params[id_INIT_L03] = Property(LUT_ONE, 4); // (unused)
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lower->params[id_INIT_L11] = Property(LUT_AND, 4);
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lower->params[id_INIT_L20] = Property(LUT_D1, 4);
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lower->params[id_INIT_L30] = Property(is_even_x ? LUT_ONE : LUT_INV_D1, 4); // OUT1 -> COMP_OUT
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lower->params[id_C_FUNCTION] = Property(C_ADDCIN, 3);
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comp->params[id_INIT_L30] = Property(is_even_x ? LUT_ONE : LUT_INV_D1, 4); // OUT1 -> COMP_OUT
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upper->params[id_INIT_L00] = Property(LUT_D1, 4); // PINY1
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upper->params[id_INIT_L01] = Property(LUT_ONE, 4); // (unused)
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upper->params[id_INIT_L10] = Property(LUT_AND, 4);
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upper->params[id_C_I1] = Property(1, 1); // PINY1 for L00
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upper->params[id_C_FUNCTION] = Property(C_ADDCIN, 3);
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upper->params[id_C_SELX] = Property(1, 1);
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upper->params[id_C_SEL_C] = Property(1, 1);
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upper->params[id_C_Y12] = Property(1, 1);
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upper->params[id_C_CX_I] = Property(1, 1);
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upper->params[id_C_CY1_I] = Property(is_even_x, 1);
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upper->params[id_C_CY2_I] = Property(1, 1);
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upper->params[id_C_PY1_I] = Property(1, 1);
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upper->params[id_C_PY2_I] = Property(1, 1);
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cplines->params[id_C_SELX] = Property(1, 1);
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cplines->params[id_C_SEL_C] = Property(1, 1);
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cplines->params[id_C_Y12] = Property(1, 1);
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cplines->params[id_C_CX_I] = Property(1, 1);
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cplines->params[id_C_CY1_I] = Property(is_even_x, 1);
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cplines->params[id_C_CY2_I] = Property(1, 1);
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cplines->params[id_C_PY1_I] = Property(1, 1);
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cplines->params[id_C_PY2_I] = Property(1, 1);
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upper->params[id_C_O1] = Property(0b11, 2); // COMB1OUT -> OUT1
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upper->params[id_C_O2] = Property(0b11, 2); // COMB2OUT -> OUT2
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@ -337,27 +356,29 @@ MultCell::MultCell(CellInfo *lower, CellInfo *upper, IdString name, bool is_msb)
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upper->params[id_C_O2] = Property(0b10, 2); // CP_OUT2 -> OUT2
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}
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MsbRoutingCell::MsbRoutingCell(CellInfo *lower, CellInfo *upper, IdString name) : lower{lower}, upper{upper}
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MsbRoutingCell::MsbRoutingCell(CellInfo *lower, CellInfo *upper, CellInfo *comp, CellInfo *cplines, IdString name)
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: lower{lower}, upper{upper}, comp{comp}, cplines{cplines}
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{
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lower->params[id_INIT_L02] = Property(LUT_ZERO, 4); // (unused)
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lower->params[id_INIT_L03] = Property(LUT_ZERO, 4); // (unused)
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lower->params[id_INIT_L11] = Property(LUT_ZERO, 4); // (unused)
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lower->params[id_INIT_L20] = Property(LUT_ZERO, 4); // (unused)
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lower->params[id_INIT_L30] = Property(LUT_ONE, 4); // zero -> COMP_OUT (L30 is inverted)
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comp->params[id_INIT_L30] = Property(LUT_ONE, 4); // zero -> COMP_OUT (L30 is inverted)
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upper->params[id_INIT_L00] = Property(LUT_D1, 4); // PINY1
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upper->params[id_INIT_L01] = Property(LUT_ZERO, 4); // (unused)
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upper->params[id_INIT_L10] = Property(LUT_D0, 4); // L00 -> COMB2OUT
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upper->params[id_C_I1] = Property(1, 1); // PINY1 for L00
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upper->params[id_C_I1] = Property(1, 1); // PINY1 for L00
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upper->params[id_C_SELX] = Property(1, 1); // COMB2OUT -> CX_VAL; PINY1 -> PX_VAL
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upper->params[id_C_SELY1] = Property(0, 1); // COMP_OUT -> PY1_VAL
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upper->params[id_C_SELY2] = Property(0, 1); // COMP_OUT -> PY2_VAL
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upper->params[id_C_SEL_P] = Property(1, 1); // PINY1 -> PX_VAL; COMP_OUT -> PY1_VAL; COMP_OUT -> PY2_VAL
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upper->params[id_C_CX_I] = Property(1, 1); // CX_VAL -> COUTX
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upper->params[id_C_PX_I] = Property(1, 1); // PX_VAL -> POUTX
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upper->params[id_C_PY1_I] = Property(1, 1); // PY1_VAL -> POUTY1
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upper->params[id_C_PY2_I] = Property(1, 1); // PY2_VAL -> POUTY2
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cplines->params[id_C_SELX] = Property(1, 1); // COMB2OUT -> CX_VAL; PINY1 -> PX_VAL
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cplines->params[id_C_SELY1] = Property(0, 1); // COMP_OUT -> PY1_VAL
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cplines->params[id_C_SELY2] = Property(0, 1); // COMP_OUT -> PY2_VAL
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cplines->params[id_C_SEL_P] = Property(1, 1); // PINY1 -> PX_VAL; COMP_OUT -> PY1_VAL; COMP_OUT -> PY2_VAL
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cplines->params[id_C_CX_I] = Property(1, 1); // CX_VAL -> COUTX
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cplines->params[id_C_PX_I] = Property(1, 1); // PX_VAL -> POUTX
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cplines->params[id_C_PY1_I] = Property(1, 1); // PY1_VAL -> POUTY1
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cplines->params[id_C_PY2_I] = Property(1, 1); // PY2_VAL -> POUTY2
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upper->params[id_C_O2] = Property(0b11, 2); // COMB2 -> OUT2
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}
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@ -392,7 +413,8 @@ void GateMatePacker::pack_mult()
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{
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auto *b_passthru_lower = create_cell_ptr(id_CPE_L2T4, ctx->idf("%s$b_passthru_lower", name.c_str(ctx)));
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auto *b_passthru_upper = create_cell_ptr(id_CPE_L2T4, ctx->idf("%s$b_passthru_upper", name.c_str(ctx)));
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auto *b_passthru_lines = create_cell_ptr(id_CPE_CPLINES, ctx->idf("%s$b_passthru_cplines", name.c_str(ctx)));
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auto *b_passthru_lines =
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create_cell_ptr(id_CPE_CPLINES, ctx->idf("%s$b_passthru_cplines", name.c_str(ctx)));
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NetInfo *comb1_conn = ctx->createNet(ctx->idf("%s$comb1", name.c_str(ctx)));
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b_passthru_lower->connectPort(id_OUT, comb1_conn);
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b_passthru_lines->connectPort(id_OUT1, comb1_conn);
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@ -406,7 +428,10 @@ void GateMatePacker::pack_mult()
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{
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auto *carry_lower = create_cell_ptr(id_CPE_LT_L, ctx->idf("%s$carry_lower", name.c_str(ctx)));
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auto *carry_upper = create_cell_ptr(id_CPE_LT_U, ctx->idf("%s$carry_upper", name.c_str(ctx)));
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col.carry = CarryGenCell{carry_lower, carry_upper, name, !is_even_x, carry_enable_cinx};
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auto *carry_comp = create_cell_ptr(id_CPE_COMP, ctx->idf("%s$carry_comp", name.c_str(ctx)));
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auto *carry_lines = create_cell_ptr(id_CPE_CPLINES, ctx->idf("%s$carry_lines", name.c_str(ctx)));
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col.carry = CarryGenCell{carry_lower, carry_upper, carry_comp, carry_lines,
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name, !is_even_x, carry_enable_cinx};
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}
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{
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@ -414,13 +439,20 @@ void GateMatePacker::pack_mult()
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create_cell_ptr(id_CPE_LT_L, ctx->idf("%s$multf%c_lower", name.c_str(ctx), is_even_x ? 'a' : 'b'));
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auto *multfab_upper =
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create_cell_ptr(id_CPE_LT_U, ctx->idf("%s$multf%c_upper", name.c_str(ctx), is_even_x ? 'a' : 'b'));
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col.multfab = MultfabCell{multfab_lower, multfab_upper, name, is_even_x, multfab_enable_cinx};
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auto *multfab_comp =
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create_cell_ptr(id_CPE_COMP, ctx->idf("%s$multf%c_comp", name.c_str(ctx), is_even_x ? 'a' : 'b'));
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auto *multfab_lines = create_cell_ptr(
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id_CPE_CPLINES, ctx->idf("%s$multf%c_cplines", name.c_str(ctx), is_even_x ? 'a' : 'b'));
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col.multfab = MultfabCell{multfab_lower, multfab_upper, multfab_comp, multfab_lines,
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name, is_even_x, multfab_enable_cinx};
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}
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{
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auto *f_route_lower = create_cell_ptr(id_CPE_LT_L, ctx->idf("%s$f_route_lower", name.c_str(ctx)));
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auto *f_route_upper = create_cell_ptr(id_CPE_LT_U, ctx->idf("%s$f_route_upper", name.c_str(ctx)));
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col.f_route = FRoutingCell{f_route_lower, f_route_upper, name, is_even_x};
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auto *f_route_comp = create_cell_ptr(id_CPE_COMP, ctx->idf("%s$f_route_comp", name.c_str(ctx)));
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auto *f_route_lines = create_cell_ptr(id_CPE_CPLINES, ctx->idf("%s$f_route_lines", name.c_str(ctx)));
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col.f_route = FRoutingCell{f_route_lower, f_route_upper, f_route_comp, f_route_lines, name, is_even_x};
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}
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||||
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for (int i = 0; i < (a_width / 2); i++) {
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|
|
@ -433,7 +465,9 @@ void GateMatePacker::pack_mult()
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{
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||||
auto *msb_route_lower = create_cell_ptr(id_CPE_LT_L, ctx->idf("%s$msb_route_lower", name.c_str(ctx)));
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auto *msb_route_upper = create_cell_ptr(id_CPE_LT_U, ctx->idf("%s$msb_route_upper", name.c_str(ctx)));
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||||
col.msb_route = MsbRoutingCell{msb_route_lower, msb_route_upper, name};
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auto *msb_route_comp = create_cell_ptr(id_CPE_COMP, ctx->idf("%s$msb_route_comp", name.c_str(ctx)));
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||||
auto *msb_route_lines = create_cell_ptr(id_CPE_CPLINES, ctx->idf("%s$msb_route_lines", name.c_str(ctx)));
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col.msb_route = MsbRoutingCell{msb_route_lower, msb_route_upper, msb_route_comp, msb_route_lines, name};
|
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}
|
||||
|
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return col;
|
||||
|
|
@ -520,12 +554,18 @@ void GateMatePacker::pack_mult()
|
|||
|
||||
constrain_cell(col.carry.lower, b, b + 1, CPE_LT_L_Z);
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constrain_cell(col.carry.upper, b, b + 1, CPE_LT_U_Z);
|
||||
constrain_cell(col.carry.comp, b, b + 1, CPE_COMP_Z);
|
||||
constrain_cell(col.carry.cplines, b, b + 1, CPE_CPLINES_Z);
|
||||
|
||||
constrain_cell(col.multfab.lower, b, b + 2, CPE_LT_L_Z);
|
||||
constrain_cell(col.multfab.upper, b, b + 2, CPE_LT_U_Z);
|
||||
constrain_cell(col.multfab.comp, b, b + 2, CPE_COMP_Z);
|
||||
constrain_cell(col.multfab.cplines, b, b + 2, CPE_CPLINES_Z);
|
||||
|
||||
constrain_cell(col.f_route.lower, b, b + 3, CPE_LT_L_Z);
|
||||
constrain_cell(col.f_route.upper, b, b + 3, CPE_LT_U_Z);
|
||||
constrain_cell(col.f_route.comp, b, b + 3, CPE_COMP_Z);
|
||||
constrain_cell(col.f_route.cplines, b, b + 3, CPE_CPLINES_Z);
|
||||
|
||||
for (size_t mult_idx = 0; mult_idx < col.mults.size(); mult_idx++) {
|
||||
constrain_cell(col.mults[mult_idx].lower, b, b + 4 + mult_idx, CPE_LT_L_Z);
|
||||
|
|
@ -534,6 +574,8 @@ void GateMatePacker::pack_mult()
|
|||
|
||||
constrain_cell(col.msb_route.lower, b, b + 4 + col.mults.size(), CPE_LT_L_Z);
|
||||
constrain_cell(col.msb_route.upper, b, b + 4 + col.mults.size(), CPE_LT_U_Z);
|
||||
constrain_cell(col.msb_route.comp, b, b + 4 + col.mults.size(), CPE_COMP_Z);
|
||||
constrain_cell(col.msb_route.cplines, b, b + 4 + col.mults.size(), CPE_CPLINES_Z);
|
||||
}
|
||||
|
||||
// Step 3: connect them.
|
||||
|
|
|
|||
Loading…
Reference in New Issue