mirror of https://github.com/YosysHQ/nextpnr.git
Merge pull request #993 from yrabbit/lw-wip-1
gowin: Add support for long wires
This commit is contained in:
myrtle
GitHub
commit
2da7caf657
206
gowin/arch.cc
206
gowin/arch.cc
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@ -19,6 +19,7 @@
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*/
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#include <boost/algorithm/string.hpp>
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#include <cells.h>
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#include <iostream>
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#include <math.h>
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#include <regex>
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@ -175,6 +176,145 @@ DecalXY Arch::getWireDecal(WireId wire) const
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return wires.at(wire).decalxy_active;
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}
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bool Arch::allocate_longwire(NetInfo *ni, int lw_idx)
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{
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NPNR_ASSERT(ni != nullptr);
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if (ni->driver.cell == nullptr) {
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return false;
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}
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if (ni->name == id("$PACKER_VCC_NET") || ni->name == id("$PACKER_GND_NET")) {
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return false;
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}
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// So far only for OBUF
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switch (ni->driver.cell->type.index) {
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case ID_ODDR: /* fall-through*/
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case ID_ODDRC: /* fall-through*/
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case ID_IOBUF: /* fall-through*/
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case ID_TBUF:
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return false;
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case ID_OBUF:
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if (getCtx()->debug) {
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log_info("Long wire for IO %s\n", nameOf(ni));
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}
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ni = ni->driver.cell->ports.at(id_I).net;
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return allocate_longwire(ni, lw_idx);
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break;
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default:
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break;
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}
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if (getCtx()->debug) {
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log_info("Requested index:%d\n", lw_idx);
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}
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if (avail_longwires == 0 || (lw_idx != -1 && (avail_longwires & (1 << lw_idx)) == 0)) {
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return false;
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}
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int longwire = lw_idx;
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if (lw_idx == -1) {
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for (longwire = 7; longwire >= 0; --longwire) {
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if (avail_longwires & (1 << longwire)) {
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break;
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}
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}
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}
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avail_longwires &= ~(1 << longwire);
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// BUFS cell
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CellInfo *bufs;
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char buf[40];
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snprintf(buf, sizeof(buf), "$PACKER_BUFS%d", longwire);
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std::unique_ptr<CellInfo> new_cell = create_generic_cell(getCtx(), id_BUFS, buf);
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bufs = new_cell.get();
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cells[bufs->name] = std::move(new_cell);
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if (lw_idx != -1) {
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bufs->cluster = bufs->name;
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bufs->constr_z = lw_idx + BelZ::bufs_0_z;
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bufs->constr_abs_z = true;
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bufs->constr_children.clear();
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}
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// old driver -> bufs LW input net
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snprintf(buf, sizeof(buf), "$PACKER_BUFS_%c", longwire + 'A');
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auto net = std::make_unique<NetInfo>(id(buf));
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NetInfo *bufs_net = net.get();
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nets[net->name] = std::move(net);
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// split the net
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CellInfo *driver_cell = ni->driver.cell;
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IdString driver_port = ni->driver.port;
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driver_cell->disconnectPort(driver_port);
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bufs->connectPort(id_O, ni);
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bufs->connectPort(id_I, bufs_net);
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driver_cell->connectPort(driver_port, bufs_net);
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if (getCtx()->debug) {
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log_info("Long wire %d was allocated\n", longwire);
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}
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return true;
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}
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void Arch::fix_longwire_bels()
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{
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// After routing, it is clear which wires and in which bus SS00 and SS40 are used and
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// in which quadrant they are routed. Here we write it in the attributes.
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for (auto &cell : cells) {
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CellInfo *ci = cell.second.get();
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if (ci->type != id_BUFS) {
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continue;
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}
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const NetInfo *ni = ci->getPort(id_O);
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if (ni == nullptr) {
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continue;
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}
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// bus wire is one of the wires
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// value does not matter, but the L/R parameter itself
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for (auto &wire : ni->wires) {
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WireId w = wires[wire.first].type;
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switch (w.hash()) {
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case ID_LWSPINETL0:
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case ID_LWSPINETL1:
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case ID_LWSPINETL2:
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case ID_LWSPINETL3:
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case ID_LWSPINETL4:
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case ID_LWSPINETL5:
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case ID_LWSPINETL6:
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case ID_LWSPINETL7:
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case ID_LWSPINEBL0:
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case ID_LWSPINEBL1:
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case ID_LWSPINEBL2:
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case ID_LWSPINEBL3:
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case ID_LWSPINEBL4:
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case ID_LWSPINEBL5:
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case ID_LWSPINEBL6:
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case ID_LWSPINEBL7:
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ci->setParam(id("L"), Property(w.str(this)));
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break;
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case ID_LWSPINETR0:
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case ID_LWSPINETR1:
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case ID_LWSPINETR2:
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case ID_LWSPINETR3:
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case ID_LWSPINETR4:
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case ID_LWSPINETR5:
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case ID_LWSPINETR6:
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case ID_LWSPINETR7:
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case ID_LWSPINEBR0:
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case ID_LWSPINEBR1:
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case ID_LWSPINEBR2:
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case ID_LWSPINEBR3:
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case ID_LWSPINEBR4:
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case ID_LWSPINEBR5:
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case ID_LWSPINEBR6:
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case ID_LWSPINEBR7:
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ci->setParam(id("R"), Property(w.str(this)));
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break;
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default:
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break;
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}
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}
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}
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}
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WireInfo &Arch::wire_info(IdString wire)
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{
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auto w = wires.find(wire);
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@ -628,6 +768,28 @@ DelayQuad Arch::getWireTypeDelay(IdString wire)
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case ID_W830:
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len = id_X8;
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break;
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case ID_LT02:
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case ID_LT13:
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glbsrc = id_SPINE_TAP_SCLK_0;
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break;
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case ID_LT01:
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case ID_LT04:
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glbsrc = id_SPINE_TAP_SCLK_1;
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break;
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case ID_LBO0:
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case ID_LBO1:
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glbsrc = id_TAP_BRANCH_SCLK;
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break;
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case ID_LB01:
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case ID_LB11:
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case ID_LB21:
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case ID_LB31:
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case ID_LB41:
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case ID_LB51:
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case ID_LB61:
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case ID_LB71:
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glbsrc = id_BRANCH_SCLK;
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break;
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case ID_GT00:
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case ID_GT10:
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glbsrc = id_SPINE_TAP_PCLK;
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@ -647,7 +809,9 @@ DelayQuad Arch::getWireTypeDelay(IdString wire)
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glbsrc = id_BRANCH_PCLK;
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break;
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default:
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if (wire.str(this).rfind("SPINE", 0) == 0) {
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if (wire.str(this).rfind("LWSPINE", 0) == 0) {
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glbsrc = IdString(ID_CENT_SPINE_SCLK);
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} else if (wire.str(this).rfind("SPINE", 0) == 0) {
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glbsrc = IdString(ID_CENT_SPINE_PCLK);
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} else if (wire.str(this).rfind("UNK", 0) == 0) {
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glbsrc = IdString(ID_PIO_CENT_PCLK);
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@ -691,7 +855,7 @@ void Arch::read_cst(std::istream &in)
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std::regex port_attrre = std::regex("([^ =;]+=[^ =;]+) *([^;]*;)");
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std::regex iobelre = std::regex("IO([TRBL])([0-9]+)\\[?([A-Z])\\]?");
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std::regex inslocre = std::regex("INS_LOC +\"([^\"]+)\" +R([0-9]+)C([0-9]+)\\[([0-9])\\]\\[([AB])\\] *;.*");
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std::regex clockre = std::regex("CLOCK_LOC +\"([^\"]+)\" +BUF([GS])[^;]*;");
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std::regex clockre = std::regex("CLOCK_LOC +\"([^\"]+)\" +BUF([GS])(\\[([0-7])\\])?[^;]*;.*");
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std::smatch match, match_attr, match_pinloc;
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std::string line, pinline;
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enum
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@ -732,15 +896,23 @@ void Arch::read_cst(std::istream &in)
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continue;
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}
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switch (cst_type) {
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case clock: { // CLOCK name BUFG|S
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case clock: { // CLOCK name BUFG|S=#
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std::string which_clock = match[2];
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std::string lw = match[4];
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int lw_idx = -1;
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if (lw.length() > 0) {
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lw_idx = atoi(lw.c_str());
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log_info("lw_idx:%d\n", lw_idx);
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}
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if (which_clock.at(0) == 'S') {
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auto ni = nets.find(net);
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if (ni == nets.end()) {
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log_info("Net %s not found\n", net.c_str(this));
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continue;
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}
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log_info("Long wires are not implemented. The %s network will use normal routing.\n", net.c_str(this));
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if (!allocate_longwire(ni->second.get(), lw_idx)) {
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log_info("Can't use the long wires. The %s network will use normal routing.\n", net.c_str(this));
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}
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} else {
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log_info("BUFG isn't supported\n");
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continue;
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@ -1021,6 +1193,31 @@ Arch::Arch(ArchArgs args) : args(args)
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bool dff = true;
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bool oddrc = false;
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switch (static_cast<ConstIds>(bel->type_id)) {
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case ID_BUFS7:
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z++; /* fall-through*/
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case ID_BUFS6:
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z++; /* fall-through*/
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case ID_BUFS5:
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z++; /* fall-through*/
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case ID_BUFS4:
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z++; /* fall-through*/
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case ID_BUFS3:
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z++; /* fall-through*/
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case ID_BUFS2:
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z++; /* fall-through*/
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case ID_BUFS1:
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z++; /* fall-through*/
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case ID_BUFS0:
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snprintf(buf, 32, "R%dC%d_BUFS%d", row + 1, col + 1, z);
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belname = id(buf);
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addBel(belname, id_BUFS, Loc(col, row, BelZ::bufs_0_z + z), false);
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portname = IdString(pairLookup(bel->ports.get(), bel->num_ports, ID_I)->src_id);
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snprintf(buf, 32, "R%dC%d_%s", row + 1, col + 1, portname.c_str(this));
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addBelInput(belname, id_I, id(buf));
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portname = IdString(pairLookup(bel->ports.get(), bel->num_ports, ID_O)->src_id);
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snprintf(buf, 32, "R%dC%d_%s", row + 1, col + 1, portname.c_str(this));
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addBelOutput(belname, id_O, id(buf));
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break;
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case ID_GSR0:
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snprintf(buf, 32, "R%dC%d_GSR0", row + 1, col + 1);
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belname = id(buf);
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@ -1675,6 +1872,7 @@ bool Arch::route()
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}
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getCtx()->settings[id_route] = 1;
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archInfoToAttributes();
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fix_longwire_bels();
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return result;
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}
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10
gowin/arch.h
10
gowin/arch.h
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@ -459,6 +459,9 @@ struct Arch : BaseArch<ArchRanges>
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void assignArchInfo() override;
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bool cellsCompatible(const CellInfo **cells, int count) const;
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bool haveBelType(int x, int y, IdString bel_type);
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bool allocate_longwire(NetInfo *ni, int lw_idx = -1);
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void fix_longwire_bels();
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// chip db version
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unsigned int const chipdb_version = 1;
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@ -475,6 +478,9 @@ struct Arch : BaseArch<ArchRanges>
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// XXX GW1NR-9 iobuf quirk
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bool gw1n9_quirk = false;
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// 8 Long wires
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uint8_t avail_longwires = 0xff;
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// Permissible combinations of modes in a single slice
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std::map<const IdString, IdString> dff_comp_mode;
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};
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@ -487,7 +493,9 @@ enum
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iologic_0_z = 20, // start Z for the IOLOGIC bels
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vcc_0_z = 277, // virtual VCC bel Z
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gnd_0_z = 278, // virtual VSS bel Z
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osc_z = 280 // Z for the oscillator bels
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osc_z = 280, // Z for the oscillator bels
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bufs_0_z = 281, // Z for long wire buffer bel
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free_z = 289 // Must be the last, one can use z starting from this value, adjust accordingly.
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};
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}
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@ -69,6 +69,9 @@ std::unique_ptr<CellInfo> create_generic_cell(Context *ctx, IdString type, std::
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new_cell->addOutput(id_G);
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} else if (type == id_VCC) {
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new_cell->addOutput(id_V);
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} else if (type == id_BUFS) {
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new_cell->addInput(id_I);
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new_cell->addOutput(id_O);
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} else {
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log_error("unable to create generic cell of type %s\n", type.c_str(ctx));
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}
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@ -679,6 +679,81 @@ X(IOBHS)
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X(IOBIS)
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X(IOBJS)
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// long wires
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X(BUFS)
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X(BUFS0)
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X(BUFS1)
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X(BUFS2)
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X(BUFS3)
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X(BUFS4)
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X(BUFS5)
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X(BUFS6)
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X(BUFS7)
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X(LWT0)
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X(LWB0)
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X(LWT1)
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X(LWB1)
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X(LWT2)
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X(LWB2)
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X(LWT3)
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X(LWB3)
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X(LWT4)
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X(LWB4)
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X(LWT5)
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X(LWB5)
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X(LWT6)
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X(LWB6)
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X(LWT7)
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X(LWB7)
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X(LWSPINETL0)
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X(LWSPINETL1)
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X(LWSPINETL2)
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X(LWSPINETL3)
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X(LWSPINETL4)
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X(LWSPINETL5)
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X(LWSPINETL6)
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X(LWSPINETL7)
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X(LWSPINETR0)
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X(LWSPINETR1)
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X(LWSPINETR2)
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X(LWSPINETR3)
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X(LWSPINETR4)
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X(LWSPINETR5)
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X(LWSPINETR6)
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X(LWSPINETR7)
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X(LWSPINEBL0)
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X(LWSPINEBL1)
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X(LWSPINEBL2)
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X(LWSPINEBL3)
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X(LWSPINEBL4)
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X(LWSPINEBL5)
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X(LWSPINEBL6)
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X(LWSPINEBL7)
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X(LWSPINEBR0)
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X(LWSPINEBR1)
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X(LWSPINEBR2)
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X(LWSPINEBR3)
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X(LWSPINEBR4)
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X(LWSPINEBR5)
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X(LWSPINEBR6)
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X(LWSPINEBR7)
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X(LWI0)
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X(LWI1)
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X(LWI2)
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X(LWI3)
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X(LWI4)
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X(LWI5)
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X(LWI6)
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X(LWI7)
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X(LWO0)
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X(LWO1)
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X(LWO2)
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X(LWO3)
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X(LWO4)
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X(LWO5)
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X(LWO6)
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X(LWO7)
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// IOLOGIC
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X(TX)
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X(XXX_VSS)
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@ -812,6 +887,11 @@ X(CENT_SPINE_PCLK)
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X(SPINE_TAP_PCLK)
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X(TAP_BRANCH_PCLK)
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X(BRANCH_PCLK)
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X(CENT_SPINE_SCLK)
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X(SPINE_TAP_SCLK_0)
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X(SPINE_TAP_SCLK_1)
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X(TAP_BRANCH_SCLK)
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X(BRANCH_SCLK)
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X(clksetpos)
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X(clkholdpos)
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X(clk_qpos)
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@ -947,9 +947,11 @@ static void pack_io(Context *ctx)
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if (constr_bel != ci->attrs.end()) {
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constr_bel_name = constr_bel->second.as_string();
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}
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constr_bel = iob->attrs.find(id_BEL);
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if (constr_bel != iob->attrs.end()) {
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constr_bel_name = constr_bel->second.as_string();
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if (iob != nullptr) {
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constr_bel = iob->attrs.find(id_BEL);
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if (constr_bel != iob->attrs.end()) {
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constr_bel_name = constr_bel->second.as_string();
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}
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}
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if (!constr_bel_name.empty()) {
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BelId constr_bel = ctx->getBelByNameStr(constr_bel_name);
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