luke
/
nextpnr
mirror of https://github.com/YosysHQ/nextpnr.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

ecp5: fix frequency constraint on bypassed PLL outputs (#1475) 

Each PLL output in ECP5 can be bypassed, which turns it into a wire
that passes through ICLK unmodified. When an outputs mux is set to
REFCLK, disregard other PLL configuration and copy the input constraint
over unchanged.
This commit is contained in:
Dave Anderson 2025-05-06 06:55:38 -07:00 committed by GitHub
parent 18c7b4070a
commit 182b77a2e8
No known key found for this signature in database
GPG Key ID: B5690EEEBB952194
1 changed files with 24 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
ecp5/pack.cc
View File

@ -2875,12 +2875,28 @@ class Ecp5Packer
log_info(" Derived VCO frequency %.1f MHz of PLL '%s' is out of legal range [400MHz, "
"800MHz]\n",
vco_freq, ci->name.c_str(ctx));
if (str_or_default(ci->params, id_OUTDIVIDER_MUXA, "DIVA") == "REFCLK")
copy_constraint(ci, id_CLKI, id_CLKOP, 1);
else
set_constraint(ci, id_CLKOP,
simple_clk_contraint(vco_period * int_or_default(ci->params, id_CLKOP_DIV, 1)));
if (str_or_default(ci->params, id_OUTDIVIDER_MUXB, "DIVB") == "REFCLK")
copy_constraint(ci, id_CLKI, id_CLKOS, 1);
else
set_constraint(ci, id_CLKOS,
simple_clk_contraint(vco_period * int_or_default(ci->params, id_CLKOS_DIV, 1)));
if (str_or_default(ci->params, id_OUTDIVIDER_MUXC, "DIVC") == "REFCLK")
copy_constraint(ci, id_CLKI, id_CLKOS2, 1);
else
set_constraint(ci, id_CLKOS2,
simple_clk_contraint(vco_period * int_or_default(ci->params, id_CLKOS2_DIV, 1)));
if (str_or_default(ci->params, id_OUTDIVIDER_MUXD, "DIVD") == "REFCLK")
copy_constraint(ci, id_CLKI, id_CLKOS3, 1);
else
set_constraint(ci, id_CLKOS3,
simple_clk_contraint(vco_period * int_or_default(ci->params, id_CLKOS3_DIV, 1)));
} else if (ci->type == id_OSCG) {