mirror of https://github.com/YosysHQ/nextpnr.git
Check if DFFs are compatible before merging
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cd1217efdb
commit
16c94acda9
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@ -205,6 +205,25 @@ void GateMateImpl::configurePlacerHeap(PlacerHeapCfg &cfg)
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cfg.placeAllAtOnce = true;
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}
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int GateMateImpl::get_dff_config(CellInfo *dff) const
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{
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int val = 0;
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val |= int_or_default(dff->params, id_C_CPE_EN, 0);
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val <<= 2;
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val |= int_or_default(dff->params, id_C_CPE_CLK, 0);
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val <<= 2;
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val |= int_or_default(dff->params, id_C_CPE_RES, 0);
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val <<= 2;
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val |= int_or_default(dff->params, id_C_CPE_SET, 0);
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val <<= 2;
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val |= int_or_default(dff->params, id_C_EN_SR, 0);
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val <<= 1;
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val |= int_or_default(dff->params, id_C_L_D, 0);
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val <<= 1;
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val |= int_or_default(dff->params, id_FF_INIT, 0);
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return val;
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}
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void GateMateImpl::assign_cell_info()
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{
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fast_cell_info.resize(ctx->cells.size());
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@ -215,20 +234,7 @@ void GateMateImpl::assign_cell_info()
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fc.ff_en = ci->getPort(id_EN);
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fc.ff_clk = ci->getPort(id_CLK);
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fc.ff_sr = ci->getPort(id_SR);
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fc.ff_config = 0;
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fc.ff_config |= int_or_default(ci->params, id_C_CPE_EN, 0);
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fc.ff_config <<= 2;
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fc.ff_config |= int_or_default(ci->params, id_C_CPE_CLK, 0);
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fc.ff_config <<= 2;
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fc.ff_config |= int_or_default(ci->params, id_C_CPE_RES, 0);
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fc.ff_config <<= 2;
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fc.ff_config |= int_or_default(ci->params, id_C_CPE_SET, 0);
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fc.ff_config <<= 2;
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fc.ff_config |= int_or_default(ci->params, id_C_EN_SR, 0);
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fc.ff_config <<= 1;
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fc.ff_config |= int_or_default(ci->params, id_C_L_D, 0);
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fc.ff_config <<= 1;
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fc.ff_config |= int_or_default(ci->params, id_FF_INIT, 0);
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fc.ff_config = get_dff_config(ci);
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fc.dff_used = true;
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}
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}
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@ -64,6 +64,8 @@ struct GateMateImpl : HimbaechelAPI
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const GateMateTileExtraDataPOD *tile_extra_data(int tile) const;
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int get_dff_config(CellInfo *dff) const;
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std::set<IdString> available_pads;
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std::map<BelId, const PadInfoPOD *> bel_to_pad;
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pool<IdString> ddr_nets;
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@ -461,11 +461,21 @@ void GateMatePacker::pack_addf()
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}
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};
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auto merge_dff = [&](CellInfo *cell, IdString port) {
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auto merge_dff = [&](CellInfo *cell, IdString port, CellInfo *other) -> CellInfo * {
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NetInfo *o = cell->getPort(port);
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if (o) {
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CellInfo *dff = net_only_drives(ctx, o, is_dff, id_D, true);
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if (dff) {
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if (other) {
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if (dff->getPort(id_CLK) != other->getPort(id_CLK))
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return nullptr;
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if (dff->getPort(id_EN) != other->getPort(id_EN))
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return nullptr;
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if (dff->getPort(id_SR) != other->getPort(id_SR))
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return nullptr;
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if (uarch->get_dff_config(dff) != uarch->get_dff_config(other))
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return nullptr;
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}
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dff->cluster = cell->cluster;
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dff->constr_abs_z = false;
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dff->constr_z = +2;
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@ -473,8 +483,10 @@ void GateMatePacker::pack_addf()
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dff->renamePort(id_D, id_DIN);
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dff->renamePort(id_Q, id_DOUT);
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dff->type = (dff->type == id_CC_DLT) ? id_CPE_LATCH : id_CPE_FF;
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return dff;
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}
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}
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return nullptr;
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};
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for (auto &grp : splitNestedVector(groups)) {
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@ -557,14 +569,15 @@ void GateMatePacker::pack_addf()
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upper->constr_abs_z = false;
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upper->constr_y = +i;
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upper->constr_z = -1;
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CellInfo *other_dff = nullptr;
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if (merged) {
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cy->movePortTo(id_S, upper, id_OUT);
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cy->renamePort(id_S2, id_OUT);
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merge_dff(upper, id_OUT);
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other_dff = merge_dff(upper, id_OUT, other_dff);
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} else {
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cy->renamePort(id_S, id_OUT);
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}
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merge_dff(cy, id_OUT);
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merge_dff(cy, id_OUT, other_dff);
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merge_input(cy, upper, id_A, id_INIT_L00, id_IN1, id_IN2);
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merge_input(cy, upper, id_B, id_INIT_L01, id_IN3, id_IN4);
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upper->params[id_INIT_L10] = Property(LUT_XOR, 4); // XOR
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