mirror of https://github.com/YosysHQ/nextpnr.git
cleanup
This commit is contained in:
Miodrag Milanovic
parent
2c787da635
commit
16251795e0
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@ -162,8 +162,6 @@ class SpeedGradeExtraData(BBAStruct):
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bba.slice(f"{context}_timings", len(self.timings))
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def convert_timing(tim):
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#print(tim.rise.min, tim.rise.max, tim.fall.min, tim.fall.max)
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#return TimingValue(tim.rise.min, tim.rise.max)
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return TimingValue(tim.rise.min, tim.rise.max, tim.fall.min, tim.fall.max)
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def set_timings(ch):
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@ -179,7 +177,6 @@ def set_timings(ch):
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if name.startswith(("sb_del_t", "im_x", "om_x", "sb_rim_xy", "edge_xy")):
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continue
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name = "timing_" + re.sub(r"[-= >]", "_", name)
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#print(name)
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tmg.get_speed_grade(speed).extra_data.add_timing(name=ch.strs.id(name), delay=convert_timing(val))
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#for k in node_tmg_names:
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# assert k in timing, f"node class {k} not found in timing data"
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@ -188,136 +185,6 @@ def set_timings(ch):
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# assert k in timing, f"pip class {k} not found in timing data"
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# tmg.set_pip_class(grade=speed, name=k, delay=convert_timing(timing[k]))
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## These groups exist only for placement, CPE_LT* are after
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## that merged or renamed to something else
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#
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#lut = ch.timing.add_cell_variant(speed, "CPE_LT_L")
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#lut.add_comb_arc("IN1", "OUT", TimingValue(416, 418)) # IN5 to OUT1
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#lut.add_comb_arc("IN2", "OUT", TimingValue(413, 422)) # IN6 to OUT1
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#lut.add_comb_arc("IN3", "OUT", TimingValue(372, 374)) # IN7 to OUT1
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#lut.add_comb_arc("IN4", "OUT", TimingValue(275, 385)) # IN8 to OUT1
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#
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#lut = ch.timing.add_cell_variant(speed, "CPE_LT_U")
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#lut.add_comb_arc("IN1", "OUT", TimingValue(479, 484)) # to OUT2
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#lut.add_comb_arc("IN2", "OUT", TimingValue(471, 488)) # to OUT2
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#lut.add_comb_arc("IN3", "OUT", TimingValue(446, 449)) # to OUT2
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#lut.add_comb_arc("IN4", "OUT", TimingValue(443, 453)) # to OUT2
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#
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#lut = ch.timing.add_cell_variant(speed, "CPE_LT")
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#lut.add_comb_arc("IN1", "OUT", TimingValue(479, 484)) # to OUT2
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#lut.add_comb_arc("IN2", "OUT", TimingValue(471, 488)) # to OUT2
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#lut.add_comb_arc("IN3", "OUT", TimingValue(446, 449)) # to OUT2
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#lut.add_comb_arc("IN4", "OUT", TimingValue(443, 453)) # to OUT2
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#
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## Final netlist timing models, used by routing and some by
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## placement as well
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#
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#lut = ch.timing.add_cell_variant(speed, "CPE_L2T4")
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#lut.add_comb_arc("IN1", "OUT", TimingValue(479, 484)) # to OUT2
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#lut.add_comb_arc("IN2", "OUT", TimingValue(471, 488)) # to OUT2
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#lut.add_comb_arc("IN3", "OUT", TimingValue(446, 449)) # to OUT2
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#lut.add_comb_arc("IN4", "OUT", TimingValue(443, 453)) # to OUT2
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#
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#lut = ch.timing.add_cell_variant(speed, "CPE_MX4")
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#lut.add_comb_arc("IN1", "OUT1", TimingValue(479, 484)) # to OUT2
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#lut.add_comb_arc("IN2", "OUT1", TimingValue(471, 488)) # to OUT2
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#lut.add_comb_arc("IN3", "OUT1", TimingValue(446, 449)) # to OUT2
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#lut.add_comb_arc("IN4", "OUT1", TimingValue(443, 453)) # to OUT2
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#lut.add_comb_arc("IN5", "OUT1", TimingValue(416, 418)) # IN5 to OUT1
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#lut.add_comb_arc("IN6", "OUT1", TimingValue(413, 422)) # IN6 to OUT1
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#lut.add_comb_arc("IN7", "OUT1", TimingValue(372, 374)) # IN7 to OUT1
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#lut.add_comb_arc("IN8", "OUT1", TimingValue(275, 385)) # IN8 to OUT1
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#
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#lut = ch.timing.add_cell_variant(speed, "CPE_ADDF")
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#lut.add_comb_arc("IN1", "OUT2", TimingValue(479, 484)) # to OUT2
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#lut.add_comb_arc("IN2", "OUT2", TimingValue(471, 488)) # to OUT2
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#lut.add_comb_arc("IN3", "OUT2", TimingValue(446, 449)) # to OUT2
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#lut.add_comb_arc("IN4", "OUT2", TimingValue(443, 453)) # to OUT2
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#lut.add_comb_arc("IN5", "OUT1", TimingValue(416, 418)) # IN5 to OUT1
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#lut.add_comb_arc("IN6", "OUT1", TimingValue(413, 422)) # IN6 to OUT1
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#lut.add_comb_arc("IN7", "OUT1", TimingValue(372, 374)) # IN7 to OUT1
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#lut.add_comb_arc("IN8", "OUT1", TimingValue(275, 385)) # IN8 to OUT1
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#lut.add_comb_arc("CINY1", "COUTY1", TimingValue(479, 484))
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#
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#lut = ch.timing.add_cell_variant(speed, "CPE_ADDF2")
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#lut.add_comb_arc("IN1", "OUT2", TimingValue(479, 484)) # to OUT2
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#lut.add_comb_arc("IN2", "OUT2", TimingValue(471, 488)) # to OUT2
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#lut.add_comb_arc("IN3", "OUT2", TimingValue(446, 449)) # to OUT2
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#lut.add_comb_arc("IN4", "OUT2", TimingValue(443, 453)) # to OUT2
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#lut.add_comb_arc("IN5", "OUT1", TimingValue(416, 418)) # IN5 to OUT1
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#lut.add_comb_arc("IN6", "OUT1", TimingValue(413, 422)) # IN6 to OUT1
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#lut.add_comb_arc("IN7", "OUT1", TimingValue(372, 374)) # IN7 to OUT1
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#lut.add_comb_arc("IN8", "OUT1", TimingValue(275, 385)) # IN8 to OUT1
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#lut.add_comb_arc("CINY1", "COUTY1", TimingValue(479, 484))
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#
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#lut = ch.timing.add_cell_variant(speed, "CPE_MULT")
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#lut.add_comb_arc("IN1", "OUT2", TimingValue(479, 484)) # to OUT2
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#lut.add_comb_arc("IN2", "OUT2", TimingValue(471, 488)) # to OUT2
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#lut.add_comb_arc("IN3", "OUT2", TimingValue(446, 449)) # to OUT2
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#lut.add_comb_arc("IN4", "OUT2", TimingValue(443, 453)) # to OUT2
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#lut.add_comb_arc("IN5", "OUT1", TimingValue(416, 418)) # IN5 to OUT1
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#lut.add_comb_arc("IN6", "OUT1", TimingValue(413, 422)) # IN6 to OUT1
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#lut.add_comb_arc("IN7", "OUT1", TimingValue(372, 374)) # IN7 to OUT1
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#lut.add_comb_arc("IN8", "OUT1", TimingValue(275, 385)) # IN8 to OUT1
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#lut.add_comb_arc("CINY1", "COUTY1", TimingValue(479, 484))
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#
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#lut = ch.timing.add_cell_variant(speed, "CPE_COMP")
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#lut.add_comb_arc("CINY1", "COUTY1", TimingValue(479, 484))
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#
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#lut = ch.timing.add_cell_variant(speed, "CPE_CPLINES")
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#lut.add_comb_arc("CINY1", "COUTY1", TimingValue(479, 484))
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#
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#dff = ch.timing.add_cell_variant(speed, "CPE_FF")
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#dff.add_setup_hold("CLK", "DIN", ClockEdge.RISING, TimingValue(60), TimingValue(50))
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#dff.add_clock_out("CLK", "DOUT", ClockEdge.RISING, TimingValue(60))
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#
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#dff = ch.timing.add_cell_variant(speed, "CPE_LATCH")
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#dff.add_setup_hold("CLK", "DIN", ClockEdge.RISING, TimingValue(60), TimingValue(50))
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#dff.add_clock_out("CLK", "DOUT", ClockEdge.RISING, TimingValue(60))
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#
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#lut = ch.timing.add_cell_variant(speed, "CPE_RAMI")
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#lut.add_comb_arc("RAM_I", "OUT", TimingValue(0, 0))
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#
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#lut = ch.timing.add_cell_variant(speed, "CPE_RAMO")
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#lut.add_comb_arc("I", "RAM_O", convert_timing(timing["comb12_RAM_O2"]))
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#
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#lut = ch.timing.add_cell_variant(speed, "CPE_RAMIO")
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#lut.add_comb_arc("I", "RAM_O", TimingValue(0, 0))
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#lut.add_comb_arc("RAM_I", "OUT", TimingValue(0, 0))
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#
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#lut = ch.timing.add_cell_variant(speed, "CPE_IBUF")
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#lut.add_comb_arc("I", "IN1", convert_timing(timing["del_IBF"] + timing["io_sel_GPIO_IN_IN1_O"]))
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#lut.add_comb_arc("I", "IN2", convert_timing(timing["del_IBF"] + timing["io_sel_GPIO_IN_IN2_O"]))
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#
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#lut = ch.timing.add_cell_variant(speed, "CPE_OBUF")
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#lut.add_comb_arc("OUT1", "O", convert_timing(timing["del_OBF"]))
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#
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#lut = ch.timing.add_cell_variant(speed, "CPE_TOBUF")
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#lut.add_comb_arc("OUT1", "O", convert_timing(timing["del_OBF"]))
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#lut.add_comb_arc("OUT3", "O", convert_timing(timing["del_TOBF_ctrl"]))
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#lut = ch.timing.add_cell_variant(speed, "CLKIN")
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#lut.add_comb_arc("CLK0", "CLK_REF0", convert_timing(timing["clkin_CLK0_I_CLK_OUT0"]))
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#lut.add_comb_arc("CLK0", "CLK_REF1", convert_timing(timing["clkin_CLK0_I_CLK_OUT1"]))
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#lut.add_comb_arc("CLK0", "CLK_REF2", convert_timing(timing["clkin_CLK0_I_CLK_OUT2"]))
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#lut.add_comb_arc("CLK0", "CLK_REF3", convert_timing(timing["clkin_CLK0_I_CLK_OUT3"]))
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#lut.add_comb_arc("CLK1", "CLK_REF0", convert_timing(timing["clkin_CLK1_I_CLK_OUT0"]))
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#lut.add_comb_arc("CLK1", "CLK_REF1", convert_timing(timing["clkin_CLK1_I_CLK_OUT1"]))
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#lut.add_comb_arc("CLK1", "CLK_REF2", convert_timing(timing["clkin_CLK1_I_CLK_OUT2"]))
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#lut.add_comb_arc("CLK1", "CLK_REF3", convert_timing(timing["clkin_CLK1_I_CLK_OUT3"]))
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#lut.add_comb_arc("CLK2", "CLK_REF0", convert_timing(timing["clkin_CLK2_I_CLK_OUT0"]))
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#lut.add_comb_arc("CLK2", "CLK_REF1", convert_timing(timing["clkin_CLK2_I_CLK_OUT1"]))
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#lut.add_comb_arc("CLK2", "CLK_REF2", convert_timing(timing["clkin_CLK2_I_CLK_OUT2"]))
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#lut.add_comb_arc("CLK2", "CLK_REF3", convert_timing(timing["clkin_CLK2_I_CLK_OUT3"]))
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#lut.add_comb_arc("CLK3", "CLK_REF0", convert_timing(timing["clkin_CLK3_I_CLK_OUT0"]))
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#lut.add_comb_arc("CLK3", "CLK_REF1", convert_timing(timing["clkin_CLK3_I_CLK_OUT1"]))
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#lut.add_comb_arc("CLK3", "CLK_REF2", convert_timing(timing["clkin_CLK3_I_CLK_OUT2"]))
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#lut.add_comb_arc("CLK3", "CLK_REF3", convert_timing(timing["clkin_CLK3_I_CLK_OUT3"]))
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#lut.add_comb_arc("SER_CLK", "CLK_REF0", convert_timing(timing["clkin_SERDES_CLK_CLK_OUT0"]))
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#lut.add_comb_arc("SER_CLK", "CLK_REF1", convert_timing(timing["clkin_SERDES_CLK_CLK_OUT1"]))
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#lut.add_comb_arc("SER_CLK", "CLK_REF2", convert_timing(timing["clkin_SERDES_CLK_CLK_OUT2"]))
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#lut.add_comb_arc("SER_CLK", "CLK_REF3", convert_timing(timing["clkin_SERDES_CLK_CLK_OUT3"]))
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EXPECTED_VERSION = 1.4
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def main():
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