luke
/
nextpnr
mirror of https://github.com/YosysHQ/nextpnr.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

handle PLL special inputs

This commit is contained in:
Miodrag Milanovic 2025-09-25 14:46:10 +02:00
parent ca287d07a0
commit 0708a7f545
3 changed files with 43 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
himbaechel/uarch/gatemate/cells.cc
View File

@ -127,6 +127,9 @@ CellInfo *GateMatePacker::create_cell_ptr(IdString type, IdString name)
add_port(id_I, PORT_IN);
} else if (type.in(id_PLL)) {
add_port(id_CLK_REF, PORT_IN);
add_port(id_USR_CLK_REF, PORT_IN);
add_port(id_USR_SEL_A_B, PORT_IN);
add_port(id_CLK_FEEDBACK, PORT_IN);
add_port(id_CLK0, PORT_OUT);
add_port(id_CLK90, PORT_OUT);
add_port(id_CLK180, PORT_OUT);

1
himbaechel/uarch/gatemate/pack.h
View File

@ -77,6 +77,7 @@ struct GateMatePacker
void dff_update_params();
void disconnect_if_gnd(CellInfo *cell, IdString input);
void pll_out(CellInfo *cell, IdString origPort, Loc fixed);
void rewire_ram_o(CellInfo *first, IdString port, CellInfo *second);
void disconnect_not_used();
void optimize_lut();

39
himbaechel/uarch/gatemate/pack_clocking.cc
View File

@ -646,6 +646,36 @@ void GateMatePacker::pack_pll()
}
}
void GateMatePacker::rewire_ram_o(CellInfo *first, IdString port, CellInfo *second)
{
NetInfo *net = first->getPort(port);
if (net && net->driver.cell) {
net = net->driver.cell->getPort(id_I);
if (net && net->driver.cell) {
uint8_t val = int_or_default(net->driver.cell->params, id_INIT_L00, 0);
switch (val) {
case LUT_ZERO:
net = net_PACKER_GND;
break;
case LUT_ONE:
net = net_PACKER_VCC;
break;
case LUT_D0:
net = net->driver.cell->getPort(id_IN1);
break;
default:
log_error("Unsupported config, rewire from '%s' port '%s'\n", first->name.c_str(ctx), port.c_str(ctx));
break;
}
second->connectPort(port, net);
} else {
log_error("Missing cell, rewire from '%s' port '%s'\n", first->name.c_str(ctx), port.c_str(ctx));
}
} else {
log_error("Missing cell, rewire from '%s' port '%s'\n", first->name.c_str(ctx), port.c_str(ctx));
}
}
void GateMatePacker::copy_clocks()
{
if (uarch->dies == 1)
@ -729,6 +759,15 @@ void GateMatePacker::copy_clocks()
pll_new->connectPorts(id_CLK180, uarch->glbout[new_die], ctx->idf("CLK180_%d", i));
if (pll->getPort(id_CLK270))
pll_new->connectPorts(id_CLK270, uarch->glbout[new_die], ctx->idf("CLK270_%d", i));
if (pll->getPort(id_USR_LOCKED_STDY_RST))
rewire_ram_o(pll, id_USR_LOCKED_STDY_RST, pll_new);
if (pll->getPort(id_USR_CLK_REF))
rewire_ram_o(pll, id_USR_CLK_REF, pll_new);
if (pll->getPort(id_USR_SEL_A_B))
rewire_ram_o(pll, id_USR_SEL_A_B, pll_new);
move_ram_o_fixed(pll_new, id_USR_LOCKED_STDY_RST, new_loc);
move_ram_o_fixed(pll_new, id_USR_CLK_REF, new_loc);
move_ram_o_fixed(pll_new, id_USR_SEL_A_B, new_loc);
}
}
// Copy GLBOUT inputs