mirror of https://github.com/YosysHQ/nextpnr.git
100 lines
3.2 KiB
C++
100 lines
3.2 KiB
C++
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/*
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* nextpnr -- Next Generation Place and Route
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*
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* Copyright (C) 2018 Clifford Wolf <clifford@clifford.at>
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* Copyright (C) 2018 David Shah <dave@ds0.me>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "bitstream.h"
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#include <vector>
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inline TileType tile_at(const Chip &chip, int x, int y)
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{
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return chip.chip_info.tile_grid[y * chip.chip_info.width + x];
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}
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void write_asc(const Chip &chip, std::ostream &out)
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{
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// [y][x][row][col]
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const ChipInfoPOD &ci = chip.chip_info;
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const BitstreamInfoPOD &bi = *ci.bits_info;
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std::vector<std::vector<std::vector<std::vector<int8_t>>>> config;
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config.resize(ci.height);
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for (int y = 0; y < ci.height; y++) {
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config.at(y).resize(ci.width);
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for (int x = 0; x < ci.width; x++) {
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TileType tile = tile_at(chip, x, y);
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int rows = bi.tiles_nonrouting[tile].rows;
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int cols = bi.tiles_nonrouting[tile].cols;
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config.at(y).at(x).resize(rows, vector<int8_t>(cols));
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}
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}
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out << ".comment from next-pnr" << std::endl;
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switch (chip.args.type) {
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case ChipArgs::LP384:
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out << ".device 384" << std::endl;
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break;
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case ChipArgs::HX1K:
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case ChipArgs::LP1K:
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out << ".device 1k" << std::endl;
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break;
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case ChipArgs::HX8K:
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case ChipArgs::LP8K:
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out << ".device 8k" << std::endl;
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break;
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case ChipArgs::UP5K:
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out << ".device 5k" << std::endl;
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break;
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default:
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assert(false);
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}
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// Write config out
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for (int y = 0; y < ci.height; y++) {
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for (int x = 0; x < ci.width; x++) {
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TileType tile = tile_at(chip, x, y);
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if (tile == TILE_NONE)
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continue;
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switch (tile) {
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case TILE_LOGIC:
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out << ".logic_tile";
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break;
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case TILE_IO:
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out << ".io_tile";
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break;
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case TILE_RAMB:
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out << ".ramb_tile";
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break;
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case TILE_RAMT:
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out << ".ramt_tile";
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break;
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default:
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assert(false);
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}
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out << " " << x << " " << y << std::endl;
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for (auto row : config.at(y).at(x)) {
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for (auto col : row) {
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if (col == 1)
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out << "1";
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else
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out << "0";
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}
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out << std::endl;
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}
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out << std::endl;
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}
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}
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}
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