mirror of https://github.com/YosysHQ/nextpnr.git
69 lines
2.0 KiB
Makefile
69 lines
2.0 KiB
Makefile
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NEXTPNR_PATH := $(shell echo ~/cat_x/nextpnr)
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NEXTPNR_BIN := $(NEXTPNR_PATH)/build/nextpnr-fpga_interchange
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BBA_PATH := $(NEXTPNR_PATH)/build/test.bin
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RAPIDWRIGHT_PATH := $(shell echo ~/cat_x/RapidWright)
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INTERCHANGE_PATH := $(NEXTPNR_PATH)/3rdparty/fpga-interchange-schema/interchange
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DEVICE := $(shell echo ~/cat_x/python-fpga-interchange/xc7a35tcpg236-1_constraints_luts.device)
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.DELETE_ON_ERROR:
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.PHONY: all debug clean
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all: build/$(DESIGN).dcp
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build:
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mkdir build
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build/$(DESIGN).netlist: build/$(DESIGN).json
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/usr/bin/time -v python3 -mfpga_interchange.yosys_json \
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--schema_dir $(INTERCHANGE_PATH) \
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--device $(DEVICE) \
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--top $(DESIGN_TOP) \
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build/$(DESIGN).json \
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build/$(DESIGN).netlist
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build/$(DESIGN)_netlist.yaml: build/$(DESIGN).netlist
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/usr/bin/time -v python3 -mfpga_interchange.convert \
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--schema_dir $(INTERCHANGE_PATH) \
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--schema logical \
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--input_format capnp \
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--output_format yaml \
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build/$(DESIGN).netlist \
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build/$(DESIGN)_netlist.yaml
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build/$(DESIGN).phys: build/$(DESIGN).netlist
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$(NEXTPNR_BIN) \
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--chipdb $(BBA_PATH) \
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--xdc $(DESIGN).xdc \
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--netlist build/$(DESIGN).netlist \
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--phys build/$(DESIGN).phys \
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--package $(PACKAGE)
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build/$(DESIGN)_phys.yaml: build/$(DESIGN).phys
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/usr/bin/time -v python3 -mfpga_interchange.convert \
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--schema_dir $(INTERCHANGE_PATH) \
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--schema physical \
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--input_format capnp \
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--output_format yaml \
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build/$(DESIGN).phys \
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build/$(DESIGN)_phys.yaml
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debug: build/$(DESIGN).netlist
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gdb --args $(NEXTPNR_BIN) \
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--chipdb $(BBA_PATH) \
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--xdc $(DESIGN).xdc \
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--netlist build/$(DESIGN).netlist \
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--phys build/$(DESIGN).phys \
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--package $(PACKAGE)
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build/$(DESIGN).dcp: build/$(DESIGN).netlist build/$(DESIGN).phys $(DESIGN).xdc
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RAPIDWRIGHT_PATH=$(RAPIDWRIGHT_PATH) \
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$(RAPIDWRIGHT_PATH)/scripts/invoke_rapidwright.sh \
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com.xilinx.rapidwright.interchange.PhysicalNetlistToDcp \
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build/$(DESIGN).netlist build/$(DESIGN).phys $(DESIGN).xdc build/$(DESIGN).dcp
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clean::
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rm -rf build
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