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nextpnr/himbaechel/uarch/gatemate/constids.inc

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Gatemate FPGA initial support (#1473) * Initial code for GateMate * Initial work on forming bitstream * Add CCF parsing * Use CCF to set IO location * Propagate errors * Restructure code * Add support for reading from config * Start adding infrastructure for reading bitstream * Fix script * GPIO initial work * Add IN1->RAM_O2 propagation * Fixed typo * Cleanup * More parameter checks * Add LVDS support * Cleanup * Keep just used connections for now * Naive lut tree CPE pack * Naive pack CC_DFF * pack DFF fixes * Handle MUX flags * Fix DFF pack * Prevent pass trough issues * Cleanup * Use device wrapper class * Update due to API changes * Use pin connection aliases * Start work on BUFG support * Fix CC_L2T5 pack * Add CPE input inverters * Constrain routes to have correct inversion state * Add clock inversion pip * Added MX2 and MX4 support * Fix script * BUFG support * debug print if route found with wrong polarity * Some CC_DFF improvements * Create reproducible chip database * Simplify inversion of special signals * Few more DFF features * Add forgotten virtual port renames * Handle muxes with constant inputs * Allow inversion for muxes * cleanup * DFF input can be constant * init DFF only when needed * cleanup * Add basic PLL support * Add some timings * Add USR_RSTN support * Display few more primitives * Use pass trough signals to validate architecture data * Use extra tile information from chip database * Updates needed for a build system changes * Implement SB_DRIVE support * Properly named configuration bits * autogenerated constids.inc * small fix * Initial code for CPE halfs * Some cleanup * make sure FFs are compatible * reverted due to db change * Merge DFF where applicable * memory allocation issue * fix * better MX2 * ram_i handling * Cleanup MX4 * Support latches * compare L_D flag as well * Move virtual pips * Naive addf pack * carry chains grouping * Keep chip database reproducible * split addf vectors * Block CPEs when GPIO is used * Prepare placement code * RAM_I/RAM_O rewrite * fix ram_i/o index * Display RAM and add new primitives * PLL wip code * CC_PLL_ADV packing * PLL handling cleanup * Add PLL comments * Keep only high fan-out BUFG * Add skeleton for tests * Utilize move_ram_o * GPIO wip * GPIO wip * PLL fixes * cleanup * FF_OBF support * Handle FF_IBF * Make SLEW FAST if not defined as in latest p_r * Make sure FF_OBF only driving GPIO * Moved pll calc into separate file * IDDR handling and started ODDR * Route DDR input for CC_ODDR * Notify error in case ODDR or IDDR are used but not with I/O pin * cleanup for CC_USR_RSTN * Extract proper RAM location for bitstream * Code cleanup * Allow auto place of pads * Use clock source flag * Configure GPIO clock signals * Handle conflicting clk * Use BUGF in proper order * Connected CLK, works without but good for debugging * CC_CFG_CTRL placement * Group RAM data 40 bytes per row * Write BRAM content * RAM wip * Use relative constraints from chipdb * fix broken build * Memory wip * Handle custom clock for memories * Support FIFO * optimize move_ram_io * Fix SR signal handling acorrding to findings * set placer beta * Pre place what we can * Revert "debug print if route found with wrong polarity" This reverts commit cf9ded2f183db0f4e85da454e5d9f2a4da3f5cfe. * Revert "Constrain routes to have correct inversion state" This reverts commit 795c284d4856ff17e37d64f013775e86f1bed803. * Remove virtual pips * Implement post processing inversion * ADDF add ability to route additional CO * Merge two ADDFs in one CPE * Added TODO * clangformat * Cleanup * Add serdes handling in config file * Cleanup * Cleanup * Cleanup * Fix in PLL handling * Fixed ADDF edge case * No need for this * Fix latch * Sanity checks * Support CC_BRAM_20K merge * Start creating testing environment * LVDS fixes * Add connection helper * Cleanup * Fix tabs * Formatting fix * Remove optimization tests for now * remove read_bitstream * removed .c_str() * Removed config parsing * using snake_case * Use bool_or_default where applicable * refactored bitstream write code * Add allow-unconstrained option * Update DFF related messages * Add clock constraint propagation --------- Co-authored-by: Lofty <dan.ravensloft@gmail.com>
2025-04-22 16:41:01 +02:00
// autogenerated items
// primitive CC_IBUF
X(CC_IBUF)
X(PIN_NAME)
X(V_IO)
X(PULLUP)
X(PULLDOWN)
X(KEEPER)
X(SCHMITT_TRIGGER)
X(DELAY_IBF)
X(FF_IBF)
X(I)
X(Y)
// primitive CC_OBUF
X(CC_OBUF)
//X(PIN_NAME)
//X(V_IO)
X(DRIVE)
X(SLEW)
X(DELAY_OBF)
X(FF_OBF)
X(A)
X(O)
// primitive CC_TOBUF
X(CC_TOBUF)
//X(PIN_NAME)
//X(V_IO)
//X(DRIVE)
//X(SLEW)
//X(PULLUP)
//X(PULLDOWN)
//X(KEEPER)
//X(DELAY_OBF)
//X(FF_OBF)
//X(A)
X(T)
//X(O)
// primitive CC_IOBUF
X(CC_IOBUF)
//X(PIN_NAME)
//X(V_IO)
//X(DRIVE)
//X(SLEW)
//X(PULLUP)
//X(PULLDOWN)
//X(KEEPER)
//X(SCHMITT_TRIGGER)
//X(DELAY_IBF)
//X(DELAY_OBF)
//X(FF_IBF)
//X(FF_OBF)
//X(A)
//X(T)
//X(Y)
X(IO)
// primitive CC_LVDS_IBUF
X(CC_LVDS_IBUF)
X(PIN_NAME_P)
X(PIN_NAME_N)
//X(V_IO)
X(LVDS_RTERM)
//X(DELAY_IBF)
//X(FF_IBF)
X(I_P)
X(I_N)
//X(Y)
// primitive CC_LVDS_OBUF
X(CC_LVDS_OBUF)
//X(PIN_NAME_P)
//X(PIN_NAME_N)
//X(V_IO)
X(LVDS_BOOST)
//X(DELAY_OBF)
//X(FF_OBF)
//X(A)
X(O_P)
X(O_N)
// primitive CC_LVDS_TOBUF
X(CC_LVDS_TOBUF)
//X(PIN_NAME_P)
//X(PIN_NAME_N)
//X(V_IO)
//X(LVDS_BOOST)
//X(DELAY_OBF)
//X(FF_OBF)
//X(A)
//X(T)
//X(O_P)
//X(O_N)
// primitive CC_LVDS_IOBUF
X(CC_LVDS_IOBUF)
//X(PIN_NAME_P)
//X(PIN_NAME_N)
//X(V_IO)
//X(LVDS_RTERM)
//X(LVDS_BOOST)
//X(DELAY_IBF)
//X(DELAY_OBF)
//X(FF_IBF)
//X(FF_OBF)
//X(A)
//X(T)
X(IO_P)
X(IO_N)
//X(Y)
// primitive CC_IDDR
X(CC_IDDR)
X(CLK_INV)
X(D)
X(CLK)
X(Q0)
X(Q1)
// primitive CC_ODDR
X(CC_ODDR)
//X(CLK_INV)
X(D0)
X(D1)
//X(CLK)
X(DDR)
X(Q)
// primitive CC_DFF
X(CC_DFF)
//X(CLK_INV)
X(EN_INV)
X(SR_INV)
X(SR_VAL)
X(INIT)
//X(D)
//X(CLK)
X(EN)
X(SR)
//X(Q)
// primitive CC_DLT
X(CC_DLT)
X(G_INV)
//X(SR_INV)
//X(SR_VAL)
//X(INIT)
//X(D)
X(G)
//X(SR)
//X(Q)
// primitive CC_LUT1
X(CC_LUT1)
//X(O)
X(I0)
//X(INIT)
// primitive CC_LUT2
X(CC_LUT2)
//X(O)
//X(I0)
X(I1)
//X(INIT)
// primitive CC_LUT3
X(CC_LUT3)
//X(O)
//X(I0)
//X(I1)
X(I2)
//X(INIT)
// primitive CC_LUT4
X(CC_LUT4)
//X(O)
//X(I0)
//X(I1)
//X(I2)
X(I3)
//X(INIT)
// primitive CC_MX2
X(CC_MX2)
//X(D0)
//X(D1)
X(S0)
//X(Y)
// primitive CC_MX4
X(CC_MX4)
//X(D0)
//X(D1)
X(D2)
X(D3)
//X(S0)
X(S1)
//X(Y)
// primitive CC_MX8
X(CC_MX8)
//X(D0)
//X(D1)
//X(D2)
//X(D3)
X(D4)
X(D5)
X(D6)
X(D7)
//X(S0)
//X(S1)
X(S2)
//X(Y)
// primitive CC_ADDF
X(CC_ADDF)
//X(A)
X(B)
X(CI)
X(CO)
X(S)
// primitive CC_MULT
X(CC_MULT)
X(A_WIDTH)
X(B_WIDTH)
X(P_WIDTH)
//X(A)
//X(B)
X(P)
// primitive CC_BUFG
X(CC_BUFG)
//X(I)
//X(O)
// primitive CC_BRAM_20K
X(CC_BRAM_20K)
X(A_DO)
X(B_DO)
X(ECC_1B_ERR)
X(ECC_2B_ERR)
X(A_CLK)
X(B_CLK)
X(A_EN)
X(B_EN)
X(A_WE)
X(B_WE)
X(A_ADDR)
X(B_ADDR)
X(A_DI)
X(B_DI)
X(A_BM)
X(B_BM)
X(LOC)
X(A_RD_WIDTH)
X(B_RD_WIDTH)
X(A_WR_WIDTH)
X(B_WR_WIDTH)
X(RAM_MODE)
X(A_WR_MODE)
X(B_WR_MODE)
X(A_CLK_INV)
X(B_CLK_INV)
X(A_EN_INV)
X(B_EN_INV)
X(A_WE_INV)
X(B_WE_INV)
X(A_DO_REG)
X(B_DO_REG)
X(ECC_EN)
X(INIT_00)
X(INIT_01)
X(INIT_02)
X(INIT_03)
X(INIT_04)
X(INIT_05)
X(INIT_06)
X(INIT_07)
X(INIT_08)
X(INIT_09)
X(INIT_0A)
X(INIT_0B)
X(INIT_0C)
X(INIT_0D)
X(INIT_0E)
X(INIT_0F)
X(INIT_10)
X(INIT_11)
X(INIT_12)
X(INIT_13)
X(INIT_14)
X(INIT_15)
X(INIT_16)
X(INIT_17)
X(INIT_18)
X(INIT_19)
X(INIT_1A)
X(INIT_1B)
X(INIT_1C)
X(INIT_1D)
X(INIT_1E)
X(INIT_1F)
X(INIT_20)
X(INIT_21)
X(INIT_22)
X(INIT_23)
X(INIT_24)
X(INIT_25)
X(INIT_26)
X(INIT_27)
X(INIT_28)
X(INIT_29)
X(INIT_2A)
X(INIT_2B)
X(INIT_2C)
X(INIT_2D)
X(INIT_2E)
X(INIT_2F)
X(INIT_30)
X(INIT_31)
X(INIT_32)
X(INIT_33)
X(INIT_34)
X(INIT_35)
X(INIT_36)
X(INIT_37)
X(INIT_38)
X(INIT_39)
X(INIT_3A)
X(INIT_3B)
X(INIT_3C)
X(INIT_3D)
X(INIT_3E)
X(INIT_3F)
// primitive CC_BRAM_40K
X(CC_BRAM_40K)
//X(A_DO)
//X(B_DO)
X(A_ECC_1B_ERR)
X(B_ECC_1B_ERR)
X(A_ECC_2B_ERR)
X(B_ECC_2B_ERR)
X(A_CO)
X(B_CO)
//X(A_CLK)
//X(B_CLK)
//X(A_EN)
//X(B_EN)
//X(A_WE)
//X(B_WE)
//X(A_ADDR)
//X(B_ADDR)
//X(A_DI)
//X(B_DI)
//X(A_BM)
//X(B_BM)
X(A_CI)
X(B_CI)
//X(LOC)
X(CAS)
//X(A_RD_WIDTH)
//X(B_RD_WIDTH)
//X(A_WR_WIDTH)
//X(B_WR_WIDTH)
//X(RAM_MODE)
//X(A_WR_MODE)
//X(B_WR_MODE)
//X(A_CLK_INV)
//X(B_CLK_INV)
//X(A_EN_INV)
//X(B_EN_INV)
//X(A_WE_INV)
//X(B_WE_INV)
//X(A_DO_REG)
//X(B_DO_REG)
X(A_ECC_EN)
X(B_ECC_EN)
//X(INIT_00)
//X(INIT_01)
//X(INIT_02)
//X(INIT_03)
//X(INIT_04)
//X(INIT_05)
//X(INIT_06)
//X(INIT_07)
//X(INIT_08)
//X(INIT_09)
//X(INIT_0A)
//X(INIT_0B)
//X(INIT_0C)
//X(INIT_0D)
//X(INIT_0E)
//X(INIT_0F)
//X(INIT_10)
//X(INIT_11)
//X(INIT_12)
//X(INIT_13)
//X(INIT_14)
//X(INIT_15)
//X(INIT_16)
//X(INIT_17)
//X(INIT_18)
//X(INIT_19)
//X(INIT_1A)
//X(INIT_1B)
//X(INIT_1C)
//X(INIT_1D)
//X(INIT_1E)
//X(INIT_1F)
//X(INIT_20)
//X(INIT_21)
//X(INIT_22)
//X(INIT_23)
//X(INIT_24)
//X(INIT_25)
//X(INIT_26)
//X(INIT_27)
//X(INIT_28)
//X(INIT_29)
//X(INIT_2A)
//X(INIT_2B)
//X(INIT_2C)
//X(INIT_2D)
//X(INIT_2E)
//X(INIT_2F)
//X(INIT_30)
//X(INIT_31)
//X(INIT_32)
//X(INIT_33)
//X(INIT_34)
//X(INIT_35)
//X(INIT_36)
//X(INIT_37)
//X(INIT_38)
//X(INIT_39)
//X(INIT_3A)
//X(INIT_3B)
//X(INIT_3C)
//X(INIT_3D)
//X(INIT_3E)
//X(INIT_3F)
X(INIT_40)
X(INIT_41)
X(INIT_42)
X(INIT_43)
X(INIT_44)
X(INIT_45)
X(INIT_46)
X(INIT_47)
X(INIT_48)
X(INIT_49)
X(INIT_4A)
X(INIT_4B)
X(INIT_4C)
X(INIT_4D)
X(INIT_4E)
X(INIT_4F)
X(INIT_50)
X(INIT_51)
X(INIT_52)
X(INIT_53)
X(INIT_54)
X(INIT_55)
X(INIT_56)
X(INIT_57)
X(INIT_58)
X(INIT_59)
X(INIT_5A)
X(INIT_5B)
X(INIT_5C)
X(INIT_5D)
X(INIT_5E)
X(INIT_5F)
X(INIT_60)
X(INIT_61)
X(INIT_62)
X(INIT_63)
X(INIT_64)
X(INIT_65)
X(INIT_66)
X(INIT_67)
X(INIT_68)
X(INIT_69)
X(INIT_6A)
X(INIT_6B)
X(INIT_6C)
X(INIT_6D)
X(INIT_6E)
X(INIT_6F)
X(INIT_70)
X(INIT_71)
X(INIT_72)
X(INIT_73)
X(INIT_74)
X(INIT_75)
X(INIT_76)
X(INIT_77)
X(INIT_78)
X(INIT_79)
X(INIT_7A)
X(INIT_7B)
X(INIT_7C)
X(INIT_7D)
X(INIT_7E)
X(INIT_7F)
// primitive CC_FIFO_40K
X(CC_FIFO_40K)
//X(A_ECC_1B_ERR)
//X(B_ECC_1B_ERR)
//X(A_ECC_2B_ERR)
//X(B_ECC_2B_ERR)
//X(A_DO)
//X(B_DO)
//X(A_CLK)
//X(A_EN)
//X(A_DI)
//X(B_DI)
//X(A_BM)
//X(B_BM)
//X(B_CLK)
//X(B_EN)
//X(B_WE)
X(F_RST_N)
X(F_ALMOST_FULL_OFFSET)
X(F_ALMOST_EMPTY_OFFSET)
X(F_FULL)
X(F_EMPTY)
X(F_ALMOST_FULL)
X(F_ALMOST_EMPTY)
X(F_RD_ERROR)
X(F_WR_ERROR)
X(F_RD_PTR)
X(F_WR_PTR)
//X(LOC)
X(DYN_STAT_SELECT)
X(ALMOST_FULL_OFFSET)
X(ALMOST_EMPTY_OFFSET)
//X(A_WIDTH)
//X(B_WIDTH)
//X(RAM_MODE)
X(FIFO_MODE)
//X(A_CLK_INV)
//X(B_CLK_INV)
//X(A_EN_INV)
//X(B_EN_INV)
//X(A_WE_INV)
//X(B_WE_INV)
//X(A_DO_REG)
//X(B_DO_REG)
//X(A_ECC_EN)
//X(B_ECC_EN)
// primitive CC_L2T4
X(CC_L2T4)
//X(O)
//X(I0)
//X(I1)
//X(I2)
//X(I3)
X(INIT_L00)
X(INIT_L01)
X(INIT_L10)
// primitive CC_L2T5
X(CC_L2T5)
//X(O)
//X(I0)
//X(I1)
//X(I2)
//X(I3)
X(I4)
X(INIT_L02)
X(INIT_L03)
X(INIT_L11)
X(INIT_L20)
// primitive CC_PLL
X(CC_PLL)
X(REF_CLK)
X(OUT_CLK)
X(PERF_MD)
X(LOCK_REQ)
X(CLK270_DOUB)
X(CLK180_DOUB)
X(LOW_JITTER)
X(CI_FILTER_CONST)
X(CP_FILTER_CONST)
X(CLK_REF)
X(CLK_FEEDBACK)
X(USR_CLK_REF)
X(USR_LOCKED_STDY_RST)
X(USR_PLL_LOCKED_STDY)
X(USR_PLL_LOCKED)
X(CLK270)
X(CLK180)
X(CLK90)
X(CLK0)
X(CLK_REF_OUT)
// primitive CC_PLL_ADV
X(CC_PLL_ADV)
X(PLL_CFG_A)
X(PLL_CFG_B)
//X(CLK_REF)
//X(CLK_FEEDBACK)
//X(USR_CLK_REF)
//X(USR_LOCKED_STDY_RST)
X(USR_SEL_A_B)
//X(USR_PLL_LOCKED_STDY)
//X(USR_PLL_LOCKED)
//X(CLK270)
//X(CLK180)
//X(CLK90)
//X(CLK0)
//X(CLK_REF_OUT)
// primitive CC_SERDES
X(CC_SERDES)
gatemate: Initial SERDES support (#1476) * Initial SERDES support * use static array for default values * Split pack into multiple files * Pre-place BUFG and related cells
2025-05-06 15:56:26 +02:00
X(RX_BUF_RESET_TIME)
X(RX_PCS_RESET_TIME)
X(RX_RESET_TIMER_PRESC)
X(RX_RESET_DONE_GATE)
X(RX_CDR_RESET_TIME)
X(RX_EQA_RESET_TIME)
X(RX_PMA_RESET_TIME)
X(RX_WAIT_CDR_LOCK)
X(RX_CALIB_EN)
X(RX_CALIB_OVR)
X(RX_CALIB_VAL)
X(RX_RTERM_VCMSEL)
X(RX_RTERM_PD)
X(RX_EQA_CKP_LF)
X(RX_EQA_CKP_HF)
X(RX_EQA_CKP_OFFSET)
X(RX_EN_EQA)
X(RX_EQA_LOCK_CFG)
X(RX_TH_MON1)
X(RX_EN_EQA_EXT_VALUE)
X(RX_TH_MON2)
X(RX_TAPW)
X(RX_AFE_OFFSET)
X(RX_EQA_CONFIG)
X(RX_AFE_PEAK)
X(RX_AFE_GAIN)
X(RX_AFE_VCMSEL)
X(RX_CDR_CKP)
X(RX_CDR_CKI)
X(RX_CDR_TRANS_TH)
X(RX_CDR_LOCK_CFG)
X(RX_CDR_FREQ_ACC)
X(RX_CDR_PHASE_ACC)
X(RX_CDR_SET_ACC_CONFIG)
X(RX_CDR_FORCE_LOCK)
X(RX_ALIGN_MCOMMA_VALUE)
X(RX_MCOMMA_ALIGN_OVR)
X(RX_MCOMMA_ALIGN)
X(RX_ALIGN_PCOMMA_VALUE)
X(RX_PCOMMA_ALIGN_OVR)
X(RX_PCOMMA_ALIGN)
X(RX_ALIGN_COMMA_WORD)
X(RX_ALIGN_COMMA_ENABLE)
X(RX_SLIDE_MODE)
X(RX_COMMA_DETECT_EN_OVR)
X(RX_COMMA_DETECT_EN)
X(RX_SLIDE)
X(RX_EYE_MEAS_EN)
X(RX_EYE_MEAS_CFG)
X(RX_MON_PH_OFFSET)
X(RX_EI_BIAS)
X(RX_EI_BW_SEL)
X(RX_EN_EI_DETECTOR_OVR)
X(RX_EN_EI_DETECTOR)
X(RX_DATA_SEL)
X(RX_BUF_BYPASS)
X(RX_CLKCOR_USE)
X(RX_CLKCOR_MIN_LAT)
X(RX_CLKCOR_MAX_LAT)
X(RX_CLKCOR_SEQ_1_0)
X(RX_CLKCOR_SEQ_1_1)
X(RX_CLKCOR_SEQ_1_2)
X(RX_CLKCOR_SEQ_1_3)
X(RX_PMA_LOOPBACK)
X(RX_PCS_LOOPBACK)
X(RX_DATAPATH_SEL)
X(RX_PRBS_OVR)
X(RX_PRBS_SEL)
X(RX_LOOPBACK_OVR)
X(RX_PRBS_CNT_RESET)
X(RX_POWER_DOWN_OVR)
X(RX_POWER_DOWN_N)
X(RX_RESET_OVR)
X(RX_RESET)
X(RX_PMA_RESET_OVR)
X(RX_PMA_RESET)
X(RX_EQA_RESET_OVR)
X(RX_EQA_RESET)
X(RX_CDR_RESET_OVR)
X(RX_CDR_RESET)
X(RX_PCS_RESET_OVR)
X(RX_PCS_RESET)
X(RX_BUF_RESET_OVR)
X(RX_BUF_RESET)
X(RX_POLARITY_OVR)
X(RX_POLARITY)
X(RX_8B10B_EN_OVR)
X(RX_8B10B_EN)
X(RX_8B10B_BYPASS)
X(RX_BYTE_REALIGN)
X(RX_DBG_EN)
X(RX_DBG_SEL)
X(RX_DBG_MODE)
X(RX_DBG_SRAM_DELAY)
X(RX_DBG_ADDR)
X(RX_DBG_RE)
X(RX_DBG_WE)
X(RX_DBG_DATA)
X(TX_SEL_PRE)
X(TX_SEL_POST)
X(TX_AMP)
X(TX_BRANCH_EN_PRE)
X(TX_BRANCH_EN_MAIN)
X(TX_BRANCH_EN_POST)
X(TX_TAIL_CASCODE)
X(TX_DC_ENABLE)
X(TX_DC_OFFSET)
X(TX_CM_RAISE)
X(TX_CM_THRESHOLD_0)
X(TX_CM_THRESHOLD_1)
X(TX_SEL_PRE_EI)
X(TX_SEL_POST_EI)
X(TX_AMP_EI)
X(TX_BRANCH_EN_PRE_EI)
X(TX_BRANCH_EN_MAIN_EI)
X(TX_BRANCH_EN_POST_EI)
X(TX_TAIL_CASCODE_EI)
X(TX_DC_ENABLE_EI)
X(TX_DC_OFFSET_EI)
X(TX_CM_RAISE_EI)
X(TX_CM_THRESHOLD_0_EI)
X(TX_CM_THRESHOLD_1_EI)
X(TX_SEL_PRE_RXDET)
X(TX_SEL_POST_RXDET)
X(TX_AMP_RXDET)
X(TX_BRANCH_EN_PRE_RXDET)
X(TX_BRANCH_EN_MAIN_RXDET)
X(TX_BRANCH_EN_POST_RXDET)
X(TX_TAIL_CASCODE_RXDET)
X(TX_DC_ENABLE_RXDET)
X(TX_DC_OFFSET_RXDET)
X(TX_CM_RAISE_RXDET)
X(TX_CM_THRESHOLD_0_RXDET)
X(TX_CM_THRESHOLD_1_RXDET)
X(TX_CALIB_EN)
X(TX_CALIB_OVR)
X(TX_CALIB_VAL)
X(TX_CM_REG_KI)
X(TX_CM_SAR_EN)
X(TX_CM_REG_EN)
X(TX_PMA_RESET_TIME)
X(TX_PCS_RESET_TIME)
X(TX_PCS_RESET_OVR)
X(TX_PCS_RESET)
X(TX_PMA_RESET_OVR)
X(TX_PMA_RESET)
X(TX_RESET_OVR)
X(TX_RESET)
X(TX_PMA_LOOPBACK)
X(TX_PCS_LOOPBACK)
X(TX_DATAPATH_SEL)
X(TX_PRBS_OVR)
X(TX_PRBS_SEL)
X(TX_PRBS_FORCE_ERR)
X(TX_LOOPBACK_OVR)
X(TX_POWER_DOWN_OVR)
X(TX_POWER_DOWN_N)
X(TX_ELEC_IDLE_OVR)
X(TX_ELEC_IDLE)
X(TX_DETECT_RX_OVR)
X(TX_DETECT_RX)
X(TX_POLARITY_OVR)
X(TX_POLARITY)
X(TX_8B10B_EN_OVR)
X(TX_8B10B_EN)
X(TX_DATA_OVR)
X(TX_DATA_CNT)
X(TX_DATA_VALID)
X(PLL_EN_ADPLL_CTRL)
X(PLL_CONFIG_SEL)
X(PLL_SET_OP_LOCK)
X(PLL_ENFORCE_LOCK)
X(PLL_DISABLE_LOCK)
X(PLL_LOCK_WINDOW)
X(PLL_FAST_LOCK)
X(PLL_SYNC_BYPASS)
X(PLL_PFD_SELECT)
X(PLL_REF_BYPASS)
X(PLL_REF_SEL)
X(PLL_REF_RTERM)
X(PLL_FCNTRL)
X(PLL_MAIN_DIVSEL)
X(PLL_OUT_DIVSEL)
X(PLL_CI)
X(PLL_CP)
X(PLL_AO)
X(PLL_SCAP)
X(PLL_FILTER_SHIFT)
X(PLL_SAR_LIMIT)
X(PLL_FT)
X(PLL_OPEN_LOOP)
X(PLL_SCAP_AUTO_CAL)
X(PLL_BISC_MODE)
X(PLL_BISC_TIMER_MAX)
X(PLL_BISC_OPT_DET_IND)
X(PLL_BISC_PFD_SEL)
X(PLL_BISC_DLY_DIR)
X(PLL_BISC_COR_DLY)
X(PLL_BISC_CAL_SIGN)
X(PLL_BISC_CAL_AUTO)
X(PLL_BISC_CP_MIN)
X(PLL_BISC_CP_MAX)
X(PLL_BISC_CP_START)
X(PLL_BISC_DLY_PFD_MON_REF)
X(PLL_BISC_DLY_PFD_MON_DIV)
X(SERDES_ENABLE)
X(SERDES_AUTO_INIT)
X(SERDES_TESTMODE)
Gatemate FPGA initial support (#1473) * Initial code for GateMate * Initial work on forming bitstream * Add CCF parsing * Use CCF to set IO location * Propagate errors * Restructure code * Add support for reading from config * Start adding infrastructure for reading bitstream * Fix script * GPIO initial work * Add IN1->RAM_O2 propagation * Fixed typo * Cleanup * More parameter checks * Add LVDS support * Cleanup * Keep just used connections for now * Naive lut tree CPE pack * Naive pack CC_DFF * pack DFF fixes * Handle MUX flags * Fix DFF pack * Prevent pass trough issues * Cleanup * Use device wrapper class * Update due to API changes * Use pin connection aliases * Start work on BUFG support * Fix CC_L2T5 pack * Add CPE input inverters * Constrain routes to have correct inversion state * Add clock inversion pip * Added MX2 and MX4 support * Fix script * BUFG support * debug print if route found with wrong polarity * Some CC_DFF improvements * Create reproducible chip database * Simplify inversion of special signals * Few more DFF features * Add forgotten virtual port renames * Handle muxes with constant inputs * Allow inversion for muxes * cleanup * DFF input can be constant * init DFF only when needed * cleanup * Add basic PLL support * Add some timings * Add USR_RSTN support * Display few more primitives * Use pass trough signals to validate architecture data * Use extra tile information from chip database * Updates needed for a build system changes * Implement SB_DRIVE support * Properly named configuration bits * autogenerated constids.inc * small fix * Initial code for CPE halfs * Some cleanup * make sure FFs are compatible * reverted due to db change * Merge DFF where applicable * memory allocation issue * fix * better MX2 * ram_i handling * Cleanup MX4 * Support latches * compare L_D flag as well * Move virtual pips * Naive addf pack * carry chains grouping * Keep chip database reproducible * split addf vectors * Block CPEs when GPIO is used * Prepare placement code * RAM_I/RAM_O rewrite * fix ram_i/o index * Display RAM and add new primitives * PLL wip code * CC_PLL_ADV packing * PLL handling cleanup * Add PLL comments * Keep only high fan-out BUFG * Add skeleton for tests * Utilize move_ram_o * GPIO wip * GPIO wip * PLL fixes * cleanup * FF_OBF support * Handle FF_IBF * Make SLEW FAST if not defined as in latest p_r * Make sure FF_OBF only driving GPIO * Moved pll calc into separate file * IDDR handling and started ODDR * Route DDR input for CC_ODDR * Notify error in case ODDR or IDDR are used but not with I/O pin * cleanup for CC_USR_RSTN * Extract proper RAM location for bitstream * Code cleanup * Allow auto place of pads * Use clock source flag * Configure GPIO clock signals * Handle conflicting clk * Use BUGF in proper order * Connected CLK, works without but good for debugging * CC_CFG_CTRL placement * Group RAM data 40 bytes per row * Write BRAM content * RAM wip * Use relative constraints from chipdb * fix broken build * Memory wip * Handle custom clock for memories * Support FIFO * optimize move_ram_io * Fix SR signal handling acorrding to findings * set placer beta * Pre place what we can * Revert "debug print if route found with wrong polarity" This reverts commit cf9ded2f183db0f4e85da454e5d9f2a4da3f5cfe. * Revert "Constrain routes to have correct inversion state" This reverts commit 795c284d4856ff17e37d64f013775e86f1bed803. * Remove virtual pips * Implement post processing inversion * ADDF add ability to route additional CO * Merge two ADDFs in one CPE * Added TODO * clangformat * Cleanup * Add serdes handling in config file * Cleanup * Cleanup * Cleanup * Fix in PLL handling * Fixed ADDF edge case * No need for this * Fix latch * Sanity checks * Support CC_BRAM_20K merge * Start creating testing environment * LVDS fixes * Add connection helper * Cleanup * Fix tabs * Formatting fix * Remove optimization tests for now * remove read_bitstream * removed .c_str() * Removed config parsing * using snake_case * Use bool_or_default where applicable * refactored bitstream write code * Add allow-unconstrained option * Update DFF related messages * Add clock constraint propagation --------- Co-authored-by: Lofty <dan.ravensloft@gmail.com>
2025-04-22 16:41:01 +02:00
X(TX_DATA_I)
X(TX_RESET_I)
X(TX_PCS_RESET_I)
X(TX_PMA_RESET_I)
X(PLL_RESET_I)
gatemate: Initial SERDES support (#1476) * Initial SERDES support * use static array for default values * Split pack into multiple files * Pre-place BUFG and related cells
2025-05-06 15:56:26 +02:00
X(TX_POWER_DOWN_N_I)
Gatemate FPGA initial support (#1473) * Initial code for GateMate * Initial work on forming bitstream * Add CCF parsing * Use CCF to set IO location * Propagate errors * Restructure code * Add support for reading from config * Start adding infrastructure for reading bitstream * Fix script * GPIO initial work * Add IN1->RAM_O2 propagation * Fixed typo * Cleanup * More parameter checks * Add LVDS support * Cleanup * Keep just used connections for now * Naive lut tree CPE pack * Naive pack CC_DFF * pack DFF fixes * Handle MUX flags * Fix DFF pack * Prevent pass trough issues * Cleanup * Use device wrapper class * Update due to API changes * Use pin connection aliases * Start work on BUFG support * Fix CC_L2T5 pack * Add CPE input inverters * Constrain routes to have correct inversion state * Add clock inversion pip * Added MX2 and MX4 support * Fix script * BUFG support * debug print if route found with wrong polarity * Some CC_DFF improvements * Create reproducible chip database * Simplify inversion of special signals * Few more DFF features * Add forgotten virtual port renames * Handle muxes with constant inputs * Allow inversion for muxes * cleanup * DFF input can be constant * init DFF only when needed * cleanup * Add basic PLL support * Add some timings * Add USR_RSTN support * Display few more primitives * Use pass trough signals to validate architecture data * Use extra tile information from chip database * Updates needed for a build system changes * Implement SB_DRIVE support * Properly named configuration bits * autogenerated constids.inc * small fix * Initial code for CPE halfs * Some cleanup * make sure FFs are compatible * reverted due to db change * Merge DFF where applicable * memory allocation issue * fix * better MX2 * ram_i handling * Cleanup MX4 * Support latches * compare L_D flag as well * Move virtual pips * Naive addf pack * carry chains grouping * Keep chip database reproducible * split addf vectors * Block CPEs when GPIO is used * Prepare placement code * RAM_I/RAM_O rewrite * fix ram_i/o index * Display RAM and add new primitives * PLL wip code * CC_PLL_ADV packing * PLL handling cleanup * Add PLL comments * Keep only high fan-out BUFG * Add skeleton for tests * Utilize move_ram_o * GPIO wip * GPIO wip * PLL fixes * cleanup * FF_OBF support * Handle FF_IBF * Make SLEW FAST if not defined as in latest p_r * Make sure FF_OBF only driving GPIO * Moved pll calc into separate file * IDDR handling and started ODDR * Route DDR input for CC_ODDR * Notify error in case ODDR or IDDR are used but not with I/O pin * cleanup for CC_USR_RSTN * Extract proper RAM location for bitstream * Code cleanup * Allow auto place of pads * Use clock source flag * Configure GPIO clock signals * Handle conflicting clk * Use BUGF in proper order * Connected CLK, works without but good for debugging * CC_CFG_CTRL placement * Group RAM data 40 bytes per row * Write BRAM content * RAM wip * Use relative constraints from chipdb * fix broken build * Memory wip * Handle custom clock for memories * Support FIFO * optimize move_ram_io * Fix SR signal handling acorrding to findings * set placer beta * Pre place what we can * Revert "debug print if route found with wrong polarity" This reverts commit cf9ded2f183db0f4e85da454e5d9f2a4da3f5cfe. * Revert "Constrain routes to have correct inversion state" This reverts commit 795c284d4856ff17e37d64f013775e86f1bed803. * Remove virtual pips * Implement post processing inversion * ADDF add ability to route additional CO * Merge two ADDFs in one CPE * Added TODO * clangformat * Cleanup * Add serdes handling in config file * Cleanup * Cleanup * Cleanup * Fix in PLL handling * Fixed ADDF edge case * No need for this * Fix latch * Sanity checks * Support CC_BRAM_20K merge * Start creating testing environment * LVDS fixes * Add connection helper * Cleanup * Fix tabs * Formatting fix * Remove optimization tests for now * remove read_bitstream * removed .c_str() * Removed config parsing * using snake_case * Use bool_or_default where applicable * refactored bitstream write code * Add allow-unconstrained option * Update DFF related messages * Add clock constraint propagation --------- Co-authored-by: Lofty <dan.ravensloft@gmail.com>
2025-04-22 16:41:01 +02:00
X(TX_POLARITY_I)
X(TX_PRBS_SEL_I)
X(TX_PRBS_FORCE_ERR_I)
X(TX_8B10B_EN_I)
X(TX_8B10B_BYPASS_I)
X(TX_CHAR_IS_K_I)
X(TX_CHAR_DISPMODE_I)
X(TX_CHAR_DISPVAL_I)
X(TX_ELEC_IDLE_I)
X(TX_DETECT_RX_I)
X(LOOPBACK_I)
gatemate: Initial SERDES support (#1476) * Initial SERDES support * use static array for default values * Split pack into multiple files * Pre-place BUFG and related cells
2025-05-06 15:56:26 +02:00
X(TX_CLK_I)
X(RX_CLK_I)
Gatemate FPGA initial support (#1473) * Initial code for GateMate * Initial work on forming bitstream * Add CCF parsing * Use CCF to set IO location * Propagate errors * Restructure code * Add support for reading from config * Start adding infrastructure for reading bitstream * Fix script * GPIO initial work * Add IN1->RAM_O2 propagation * Fixed typo * Cleanup * More parameter checks * Add LVDS support * Cleanup * Keep just used connections for now * Naive lut tree CPE pack * Naive pack CC_DFF * pack DFF fixes * Handle MUX flags * Fix DFF pack * Prevent pass trough issues * Cleanup * Use device wrapper class * Update due to API changes * Use pin connection aliases * Start work on BUFG support * Fix CC_L2T5 pack * Add CPE input inverters * Constrain routes to have correct inversion state * Add clock inversion pip * Added MX2 and MX4 support * Fix script * BUFG support * debug print if route found with wrong polarity * Some CC_DFF improvements * Create reproducible chip database * Simplify inversion of special signals * Few more DFF features * Add forgotten virtual port renames * Handle muxes with constant inputs * Allow inversion for muxes * cleanup * DFF input can be constant * init DFF only when needed * cleanup * Add basic PLL support * Add some timings * Add USR_RSTN support * Display few more primitives * Use pass trough signals to validate architecture data * Use extra tile information from chip database * Updates needed for a build system changes * Implement SB_DRIVE support * Properly named configuration bits * autogenerated constids.inc * small fix * Initial code for CPE halfs * Some cleanup * make sure FFs are compatible * reverted due to db change * Merge DFF where applicable * memory allocation issue * fix * better MX2 * ram_i handling * Cleanup MX4 * Support latches * compare L_D flag as well * Move virtual pips * Naive addf pack * carry chains grouping * Keep chip database reproducible * split addf vectors * Block CPEs when GPIO is used * Prepare placement code * RAM_I/RAM_O rewrite * fix ram_i/o index * Display RAM and add new primitives * PLL wip code * CC_PLL_ADV packing * PLL handling cleanup * Add PLL comments * Keep only high fan-out BUFG * Add skeleton for tests * Utilize move_ram_o * GPIO wip * GPIO wip * PLL fixes * cleanup * FF_OBF support * Handle FF_IBF * Make SLEW FAST if not defined as in latest p_r * Make sure FF_OBF only driving GPIO * Moved pll calc into separate file * IDDR handling and started ODDR * Route DDR input for CC_ODDR * Notify error in case ODDR or IDDR are used but not with I/O pin * cleanup for CC_USR_RSTN * Extract proper RAM location for bitstream * Code cleanup * Allow auto place of pads * Use clock source flag * Configure GPIO clock signals * Handle conflicting clk * Use BUGF in proper order * Connected CLK, works without but good for debugging * CC_CFG_CTRL placement * Group RAM data 40 bytes per row * Write BRAM content * RAM wip * Use relative constraints from chipdb * fix broken build * Memory wip * Handle custom clock for memories * Support FIFO * optimize move_ram_io * Fix SR signal handling acorrding to findings * set placer beta * Pre place what we can * Revert "debug print if route found with wrong polarity" This reverts commit cf9ded2f183db0f4e85da454e5d9f2a4da3f5cfe. * Revert "Constrain routes to have correct inversion state" This reverts commit 795c284d4856ff17e37d64f013775e86f1bed803. * Remove virtual pips * Implement post processing inversion * ADDF add ability to route additional CO * Merge two ADDFs in one CPE * Added TODO * clangformat * Cleanup * Add serdes handling in config file * Cleanup * Cleanup * Cleanup * Fix in PLL handling * Fixed ADDF edge case * No need for this * Fix latch * Sanity checks * Support CC_BRAM_20K merge * Start creating testing environment * LVDS fixes * Add connection helper * Cleanup * Fix tabs * Formatting fix * Remove optimization tests for now * remove read_bitstream * removed .c_str() * Removed config parsing * using snake_case * Use bool_or_default where applicable * refactored bitstream write code * Add allow-unconstrained option * Update DFF related messages * Add clock constraint propagation --------- Co-authored-by: Lofty <dan.ravensloft@gmail.com>
2025-04-22 16:41:01 +02:00
X(RX_RESET_I)
X(RX_PMA_RESET_I)
X(RX_EQA_RESET_I)
X(RX_CDR_RESET_I)
X(RX_PCS_RESET_I)
X(RX_BUF_RESET_I)
gatemate: Initial SERDES support (#1476) * Initial SERDES support * use static array for default values * Split pack into multiple files * Pre-place BUFG and related cells
2025-05-06 15:56:26 +02:00
X(RX_POWER_DOWN_N_I)
Gatemate FPGA initial support (#1473) * Initial code for GateMate * Initial work on forming bitstream * Add CCF parsing * Use CCF to set IO location * Propagate errors * Restructure code * Add support for reading from config * Start adding infrastructure for reading bitstream * Fix script * GPIO initial work * Add IN1->RAM_O2 propagation * Fixed typo * Cleanup * More parameter checks * Add LVDS support * Cleanup * Keep just used connections for now * Naive lut tree CPE pack * Naive pack CC_DFF * pack DFF fixes * Handle MUX flags * Fix DFF pack * Prevent pass trough issues * Cleanup * Use device wrapper class * Update due to API changes * Use pin connection aliases * Start work on BUFG support * Fix CC_L2T5 pack * Add CPE input inverters * Constrain routes to have correct inversion state * Add clock inversion pip * Added MX2 and MX4 support * Fix script * BUFG support * debug print if route found with wrong polarity * Some CC_DFF improvements * Create reproducible chip database * Simplify inversion of special signals * Few more DFF features * Add forgotten virtual port renames * Handle muxes with constant inputs * Allow inversion for muxes * cleanup * DFF input can be constant * init DFF only when needed * cleanup * Add basic PLL support * Add some timings * Add USR_RSTN support * Display few more primitives * Use pass trough signals to validate architecture data * Use extra tile information from chip database * Updates needed for a build system changes * Implement SB_DRIVE support * Properly named configuration bits * autogenerated constids.inc * small fix * Initial code for CPE halfs * Some cleanup * make sure FFs are compatible * reverted due to db change * Merge DFF where applicable * memory allocation issue * fix * better MX2 * ram_i handling * Cleanup MX4 * Support latches * compare L_D flag as well * Move virtual pips * Naive addf pack * carry chains grouping * Keep chip database reproducible * split addf vectors * Block CPEs when GPIO is used * Prepare placement code * RAM_I/RAM_O rewrite * fix ram_i/o index * Display RAM and add new primitives * PLL wip code * CC_PLL_ADV packing * PLL handling cleanup * Add PLL comments * Keep only high fan-out BUFG * Add skeleton for tests * Utilize move_ram_o * GPIO wip * GPIO wip * PLL fixes * cleanup * FF_OBF support * Handle FF_IBF * Make SLEW FAST if not defined as in latest p_r * Make sure FF_OBF only driving GPIO * Moved pll calc into separate file * IDDR handling and started ODDR * Route DDR input for CC_ODDR * Notify error in case ODDR or IDDR are used but not with I/O pin * cleanup for CC_USR_RSTN * Extract proper RAM location for bitstream * Code cleanup * Allow auto place of pads * Use clock source flag * Configure GPIO clock signals * Handle conflicting clk * Use BUGF in proper order * Connected CLK, works without but good for debugging * CC_CFG_CTRL placement * Group RAM data 40 bytes per row * Write BRAM content * RAM wip * Use relative constraints from chipdb * fix broken build * Memory wip * Handle custom clock for memories * Support FIFO * optimize move_ram_io * Fix SR signal handling acorrding to findings * set placer beta * Pre place what we can * Revert "debug print if route found with wrong polarity" This reverts commit cf9ded2f183db0f4e85da454e5d9f2a4da3f5cfe. * Revert "Constrain routes to have correct inversion state" This reverts commit 795c284d4856ff17e37d64f013775e86f1bed803. * Remove virtual pips * Implement post processing inversion * ADDF add ability to route additional CO * Merge two ADDFs in one CPE * Added TODO * clangformat * Cleanup * Add serdes handling in config file * Cleanup * Cleanup * Cleanup * Fix in PLL handling * Fixed ADDF edge case * No need for this * Fix latch * Sanity checks * Support CC_BRAM_20K merge * Start creating testing environment * LVDS fixes * Add connection helper * Cleanup * Fix tabs * Formatting fix * Remove optimization tests for now * remove read_bitstream * removed .c_str() * Removed config parsing * using snake_case * Use bool_or_default where applicable * refactored bitstream write code * Add allow-unconstrained option * Update DFF related messages * Add clock constraint propagation --------- Co-authored-by: Lofty <dan.ravensloft@gmail.com>
2025-04-22 16:41:01 +02:00
X(RX_POLARITY_I)
X(RX_PRBS_SEL_I)
X(RX_PRBS_CNT_RESET_I)
X(RX_8B10B_EN_I)
X(RX_8B10B_BYPASS_I)
X(RX_EN_EI_DETECTOR_I)
X(RX_COMMA_DETECT_EN_I)
X(RX_SLIDE_I)
X(RX_MCOMMA_ALIGN_I)
X(RX_PCOMMA_ALIGN_I)
gatemate: Initial SERDES support (#1476) * Initial SERDES support * use static array for default values * Split pack into multiple files * Pre-place BUFG and related cells
2025-05-06 15:56:26 +02:00
X(REGFILE_CLK_I)
Gatemate FPGA initial support (#1473) * Initial code for GateMate * Initial work on forming bitstream * Add CCF parsing * Use CCF to set IO location * Propagate errors * Restructure code * Add support for reading from config * Start adding infrastructure for reading bitstream * Fix script * GPIO initial work * Add IN1->RAM_O2 propagation * Fixed typo * Cleanup * More parameter checks * Add LVDS support * Cleanup * Keep just used connections for now * Naive lut tree CPE pack * Naive pack CC_DFF * pack DFF fixes * Handle MUX flags * Fix DFF pack * Prevent pass trough issues * Cleanup * Use device wrapper class * Update due to API changes * Use pin connection aliases * Start work on BUFG support * Fix CC_L2T5 pack * Add CPE input inverters * Constrain routes to have correct inversion state * Add clock inversion pip * Added MX2 and MX4 support * Fix script * BUFG support * debug print if route found with wrong polarity * Some CC_DFF improvements * Create reproducible chip database * Simplify inversion of special signals * Few more DFF features * Add forgotten virtual port renames * Handle muxes with constant inputs * Allow inversion for muxes * cleanup * DFF input can be constant * init DFF only when needed * cleanup * Add basic PLL support * Add some timings * Add USR_RSTN support * Display few more primitives * Use pass trough signals to validate architecture data * Use extra tile information from chip database * Updates needed for a build system changes * Implement SB_DRIVE support * Properly named configuration bits * autogenerated constids.inc * small fix * Initial code for CPE halfs * Some cleanup * make sure FFs are compatible * reverted due to db change * Merge DFF where applicable * memory allocation issue * fix * better MX2 * ram_i handling * Cleanup MX4 * Support latches * compare L_D flag as well * Move virtual pips * Naive addf pack * carry chains grouping * Keep chip database reproducible * split addf vectors * Block CPEs when GPIO is used * Prepare placement code * RAM_I/RAM_O rewrite * fix ram_i/o index * Display RAM and add new primitives * PLL wip code * CC_PLL_ADV packing * PLL handling cleanup * Add PLL comments * Keep only high fan-out BUFG * Add skeleton for tests * Utilize move_ram_o * GPIO wip * GPIO wip * PLL fixes * cleanup * FF_OBF support * Handle FF_IBF * Make SLEW FAST if not defined as in latest p_r * Make sure FF_OBF only driving GPIO * Moved pll calc into separate file * IDDR handling and started ODDR * Route DDR input for CC_ODDR * Notify error in case ODDR or IDDR are used but not with I/O pin * cleanup for CC_USR_RSTN * Extract proper RAM location for bitstream * Code cleanup * Allow auto place of pads * Use clock source flag * Configure GPIO clock signals * Handle conflicting clk * Use BUGF in proper order * Connected CLK, works without but good for debugging * CC_CFG_CTRL placement * Group RAM data 40 bytes per row * Write BRAM content * RAM wip * Use relative constraints from chipdb * fix broken build * Memory wip * Handle custom clock for memories * Support FIFO * optimize move_ram_io * Fix SR signal handling acorrding to findings * set placer beta * Pre place what we can * Revert "debug print if route found with wrong polarity" This reverts commit cf9ded2f183db0f4e85da454e5d9f2a4da3f5cfe. * Revert "Constrain routes to have correct inversion state" This reverts commit 795c284d4856ff17e37d64f013775e86f1bed803. * Remove virtual pips * Implement post processing inversion * ADDF add ability to route additional CO * Merge two ADDFs in one CPE * Added TODO * clangformat * Cleanup * Add serdes handling in config file * Cleanup * Cleanup * Cleanup * Fix in PLL handling * Fixed ADDF edge case * No need for this * Fix latch * Sanity checks * Support CC_BRAM_20K merge * Start creating testing environment * LVDS fixes * Add connection helper * Cleanup * Fix tabs * Formatting fix * Remove optimization tests for now * remove read_bitstream * removed .c_str() * Removed config parsing * using snake_case * Use bool_or_default where applicable * refactored bitstream write code * Add allow-unconstrained option * Update DFF related messages * Add clock constraint propagation --------- Co-authored-by: Lofty <dan.ravensloft@gmail.com>
2025-04-22 16:41:01 +02:00
X(REGFILE_WE_I)
X(REGFILE_EN_I)
X(REGFILE_ADDR_I)
X(REGFILE_DI_I)
X(REGFILE_MASK_I)
X(RX_DATA_O)
X(RX_NOT_IN_TABLE_O)
X(RX_CHAR_IS_COMMA_O)
X(RX_CHAR_IS_K_O)
X(RX_DISP_ERR_O)
gatemate: Initial SERDES support (#1476) * Initial SERDES support * use static array for default values * Split pack into multiple files * Pre-place BUFG and related cells
2025-05-06 15:56:26 +02:00
X(TX_DETECT_RX_DONE_O)
X(TX_DETECT_RX_PRESENT_O)
Gatemate FPGA initial support (#1473) * Initial code for GateMate * Initial work on forming bitstream * Add CCF parsing * Use CCF to set IO location * Propagate errors * Restructure code * Add support for reading from config * Start adding infrastructure for reading bitstream * Fix script * GPIO initial work * Add IN1->RAM_O2 propagation * Fixed typo * Cleanup * More parameter checks * Add LVDS support * Cleanup * Keep just used connections for now * Naive lut tree CPE pack * Naive pack CC_DFF * pack DFF fixes * Handle MUX flags * Fix DFF pack * Prevent pass trough issues * Cleanup * Use device wrapper class * Update due to API changes * Use pin connection aliases * Start work on BUFG support * Fix CC_L2T5 pack * Add CPE input inverters * Constrain routes to have correct inversion state * Add clock inversion pip * Added MX2 and MX4 support * Fix script * BUFG support * debug print if route found with wrong polarity * Some CC_DFF improvements * Create reproducible chip database * Simplify inversion of special signals * Few more DFF features * Add forgotten virtual port renames * Handle muxes with constant inputs * Allow inversion for muxes * cleanup * DFF input can be constant * init DFF only when needed * cleanup * Add basic PLL support * Add some timings * Add USR_RSTN support * Display few more primitives * Use pass trough signals to validate architecture data * Use extra tile information from chip database * Updates needed for a build system changes * Implement SB_DRIVE support * Properly named configuration bits * autogenerated constids.inc * small fix * Initial code for CPE halfs * Some cleanup * make sure FFs are compatible * reverted due to db change * Merge DFF where applicable * memory allocation issue * fix * better MX2 * ram_i handling * Cleanup MX4 * Support latches * compare L_D flag as well * Move virtual pips * Naive addf pack * carry chains grouping * Keep chip database reproducible * split addf vectors * Block CPEs when GPIO is used * Prepare placement code * RAM_I/RAM_O rewrite * fix ram_i/o index * Display RAM and add new primitives * PLL wip code * CC_PLL_ADV packing * PLL handling cleanup * Add PLL comments * Keep only high fan-out BUFG * Add skeleton for tests * Utilize move_ram_o * GPIO wip * GPIO wip * PLL fixes * cleanup * FF_OBF support * Handle FF_IBF * Make SLEW FAST if not defined as in latest p_r * Make sure FF_OBF only driving GPIO * Moved pll calc into separate file * IDDR handling and started ODDR * Route DDR input for CC_ODDR * Notify error in case ODDR or IDDR are used but not with I/O pin * cleanup for CC_USR_RSTN * Extract proper RAM location for bitstream * Code cleanup * Allow auto place of pads * Use clock source flag * Configure GPIO clock signals * Handle conflicting clk * Use BUGF in proper order * Connected CLK, works without but good for debugging * CC_CFG_CTRL placement * Group RAM data 40 bytes per row * Write BRAM content * RAM wip * Use relative constraints from chipdb * fix broken build * Memory wip * Handle custom clock for memories * Support FIFO * optimize move_ram_io * Fix SR signal handling acorrding to findings * set placer beta * Pre place what we can * Revert "debug print if route found with wrong polarity" This reverts commit cf9ded2f183db0f4e85da454e5d9f2a4da3f5cfe. * Revert "Constrain routes to have correct inversion state" This reverts commit 795c284d4856ff17e37d64f013775e86f1bed803. * Remove virtual pips * Implement post processing inversion * ADDF add ability to route additional CO * Merge two ADDFs in one CPE * Added TODO * clangformat * Cleanup * Add serdes handling in config file * Cleanup * Cleanup * Cleanup * Fix in PLL handling * Fixed ADDF edge case * No need for this * Fix latch * Sanity checks * Support CC_BRAM_20K merge * Start creating testing environment * LVDS fixes * Add connection helper * Cleanup * Fix tabs * Formatting fix * Remove optimization tests for now * remove read_bitstream * removed .c_str() * Removed config parsing * using snake_case * Use bool_or_default where applicable * refactored bitstream write code * Add allow-unconstrained option * Update DFF related messages * Add clock constraint propagation --------- Co-authored-by: Lofty <dan.ravensloft@gmail.com>
2025-04-22 16:41:01 +02:00
X(TX_BUF_ERR_O)
gatemate: Initial SERDES support (#1476) * Initial SERDES support * use static array for default values * Split pack into multiple files * Pre-place BUFG and related cells
2025-05-06 15:56:26 +02:00
X(TX_RESET_DONE_O)
Gatemate FPGA initial support (#1473) * Initial code for GateMate * Initial work on forming bitstream * Add CCF parsing * Use CCF to set IO location * Propagate errors * Restructure code * Add support for reading from config * Start adding infrastructure for reading bitstream * Fix script * GPIO initial work * Add IN1->RAM_O2 propagation * Fixed typo * Cleanup * More parameter checks * Add LVDS support * Cleanup * Keep just used connections for now * Naive lut tree CPE pack * Naive pack CC_DFF * pack DFF fixes * Handle MUX flags * Fix DFF pack * Prevent pass trough issues * Cleanup * Use device wrapper class * Update due to API changes * Use pin connection aliases * Start work on BUFG support * Fix CC_L2T5 pack * Add CPE input inverters * Constrain routes to have correct inversion state * Add clock inversion pip * Added MX2 and MX4 support * Fix script * BUFG support * debug print if route found with wrong polarity * Some CC_DFF improvements * Create reproducible chip database * Simplify inversion of special signals * Few more DFF features * Add forgotten virtual port renames * Handle muxes with constant inputs * Allow inversion for muxes * cleanup * DFF input can be constant * init DFF only when needed * cleanup * Add basic PLL support * Add some timings * Add USR_RSTN support * Display few more primitives * Use pass trough signals to validate architecture data * Use extra tile information from chip database * Updates needed for a build system changes * Implement SB_DRIVE support * Properly named configuration bits * autogenerated constids.inc * small fix * Initial code for CPE halfs * Some cleanup * make sure FFs are compatible * reverted due to db change * Merge DFF where applicable * memory allocation issue * fix * better MX2 * ram_i handling * Cleanup MX4 * Support latches * compare L_D flag as well * Move virtual pips * Naive addf pack * carry chains grouping * Keep chip database reproducible * split addf vectors * Block CPEs when GPIO is used * Prepare placement code * RAM_I/RAM_O rewrite * fix ram_i/o index * Display RAM and add new primitives * PLL wip code * CC_PLL_ADV packing * PLL handling cleanup * Add PLL comments * Keep only high fan-out BUFG * Add skeleton for tests * Utilize move_ram_o * GPIO wip * GPIO wip * PLL fixes * cleanup * FF_OBF support * Handle FF_IBF * Make SLEW FAST if not defined as in latest p_r * Make sure FF_OBF only driving GPIO * Moved pll calc into separate file * IDDR handling and started ODDR * Route DDR input for CC_ODDR * Notify error in case ODDR or IDDR are used but not with I/O pin * cleanup for CC_USR_RSTN * Extract proper RAM location for bitstream * Code cleanup * Allow auto place of pads * Use clock source flag * Configure GPIO clock signals * Handle conflicting clk * Use BUGF in proper order * Connected CLK, works without but good for debugging * CC_CFG_CTRL placement * Group RAM data 40 bytes per row * Write BRAM content * RAM wip * Use relative constraints from chipdb * fix broken build * Memory wip * Handle custom clock for memories * Support FIFO * optimize move_ram_io * Fix SR signal handling acorrding to findings * set placer beta * Pre place what we can * Revert "debug print if route found with wrong polarity" This reverts commit cf9ded2f183db0f4e85da454e5d9f2a4da3f5cfe. * Revert "Constrain routes to have correct inversion state" This reverts commit 795c284d4856ff17e37d64f013775e86f1bed803. * Remove virtual pips * Implement post processing inversion * ADDF add ability to route additional CO * Merge two ADDFs in one CPE * Added TODO * clangformat * Cleanup * Add serdes handling in config file * Cleanup * Cleanup * Cleanup * Fix in PLL handling * Fixed ADDF edge case * No need for this * Fix latch * Sanity checks * Support CC_BRAM_20K merge * Start creating testing environment * LVDS fixes * Add connection helper * Cleanup * Fix tabs * Formatting fix * Remove optimization tests for now * remove read_bitstream * removed .c_str() * Removed config parsing * using snake_case * Use bool_or_default where applicable * refactored bitstream write code * Add allow-unconstrained option * Update DFF related messages * Add clock constraint propagation --------- Co-authored-by: Lofty <dan.ravensloft@gmail.com>
2025-04-22 16:41:01 +02:00
X(RX_PRBS_ERR_O)
X(RX_BUF_ERR_O)
X(RX_BYTE_IS_ALIGNED_O)
X(RX_BYTE_REALIGN_O)
gatemate: Initial SERDES support (#1476) * Initial SERDES support * use static array for default values * Split pack into multiple files * Pre-place BUFG and related cells
2025-05-06 15:56:26 +02:00
X(RX_RESET_DONE_O)
Gatemate FPGA initial support (#1473) * Initial code for GateMate * Initial work on forming bitstream * Add CCF parsing * Use CCF to set IO location * Propagate errors * Restructure code * Add support for reading from config * Start adding infrastructure for reading bitstream * Fix script * GPIO initial work * Add IN1->RAM_O2 propagation * Fixed typo * Cleanup * More parameter checks * Add LVDS support * Cleanup * Keep just used connections for now * Naive lut tree CPE pack * Naive pack CC_DFF * pack DFF fixes * Handle MUX flags * Fix DFF pack * Prevent pass trough issues * Cleanup * Use device wrapper class * Update due to API changes * Use pin connection aliases * Start work on BUFG support * Fix CC_L2T5 pack * Add CPE input inverters * Constrain routes to have correct inversion state * Add clock inversion pip * Added MX2 and MX4 support * Fix script * BUFG support * debug print if route found with wrong polarity * Some CC_DFF improvements * Create reproducible chip database * Simplify inversion of special signals * Few more DFF features * Add forgotten virtual port renames * Handle muxes with constant inputs * Allow inversion for muxes * cleanup * DFF input can be constant * init DFF only when needed * cleanup * Add basic PLL support * Add some timings * Add USR_RSTN support * Display few more primitives * Use pass trough signals to validate architecture data * Use extra tile information from chip database * Updates needed for a build system changes * Implement SB_DRIVE support * Properly named configuration bits * autogenerated constids.inc * small fix * Initial code for CPE halfs * Some cleanup * make sure FFs are compatible * reverted due to db change * Merge DFF where applicable * memory allocation issue * fix * better MX2 * ram_i handling * Cleanup MX4 * Support latches * compare L_D flag as well * Move virtual pips * Naive addf pack * carry chains grouping * Keep chip database reproducible * split addf vectors * Block CPEs when GPIO is used * Prepare placement code * RAM_I/RAM_O rewrite * fix ram_i/o index * Display RAM and add new primitives * PLL wip code * CC_PLL_ADV packing * PLL handling cleanup * Add PLL comments * Keep only high fan-out BUFG * Add skeleton for tests * Utilize move_ram_o * GPIO wip * GPIO wip * PLL fixes * cleanup * FF_OBF support * Handle FF_IBF * Make SLEW FAST if not defined as in latest p_r * Make sure FF_OBF only driving GPIO * Moved pll calc into separate file * IDDR handling and started ODDR * Route DDR input for CC_ODDR * Notify error in case ODDR or IDDR are used but not with I/O pin * cleanup for CC_USR_RSTN * Extract proper RAM location for bitstream * Code cleanup * Allow auto place of pads * Use clock source flag * Configure GPIO clock signals * Handle conflicting clk * Use BUGF in proper order * Connected CLK, works without but good for debugging * CC_CFG_CTRL placement * Group RAM data 40 bytes per row * Write BRAM content * RAM wip * Use relative constraints from chipdb * fix broken build * Memory wip * Handle custom clock for memories * Support FIFO * optimize move_ram_io * Fix SR signal handling acorrding to findings * set placer beta * Pre place what we can * Revert "debug print if route found with wrong polarity" This reverts commit cf9ded2f183db0f4e85da454e5d9f2a4da3f5cfe. * Revert "Constrain routes to have correct inversion state" This reverts commit 795c284d4856ff17e37d64f013775e86f1bed803. * Remove virtual pips * Implement post processing inversion * ADDF add ability to route additional CO * Merge two ADDFs in one CPE * Added TODO * clangformat * Cleanup * Add serdes handling in config file * Cleanup * Cleanup * Cleanup * Fix in PLL handling * Fixed ADDF edge case * No need for this * Fix latch * Sanity checks * Support CC_BRAM_20K merge * Start creating testing environment * LVDS fixes * Add connection helper * Cleanup * Fix tabs * Formatting fix * Remove optimization tests for now * remove read_bitstream * removed .c_str() * Removed config parsing * using snake_case * Use bool_or_default where applicable * refactored bitstream write code * Add allow-unconstrained option * Update DFF related messages * Add clock constraint propagation --------- Co-authored-by: Lofty <dan.ravensloft@gmail.com>
2025-04-22 16:41:01 +02:00
X(RX_EI_EN_O)
gatemate: Initial SERDES support (#1476) * Initial SERDES support * use static array for default values * Split pack into multiple files * Pre-place BUFG and related cells
2025-05-06 15:56:26 +02:00
X(RX_CLK_O)
X(PLL_CLK_O)
Gatemate FPGA initial support (#1473) * Initial code for GateMate * Initial work on forming bitstream * Add CCF parsing * Use CCF to set IO location * Propagate errors * Restructure code * Add support for reading from config * Start adding infrastructure for reading bitstream * Fix script * GPIO initial work * Add IN1->RAM_O2 propagation * Fixed typo * Cleanup * More parameter checks * Add LVDS support * Cleanup * Keep just used connections for now * Naive lut tree CPE pack * Naive pack CC_DFF * pack DFF fixes * Handle MUX flags * Fix DFF pack * Prevent pass trough issues * Cleanup * Use device wrapper class * Update due to API changes * Use pin connection aliases * Start work on BUFG support * Fix CC_L2T5 pack * Add CPE input inverters * Constrain routes to have correct inversion state * Add clock inversion pip * Added MX2 and MX4 support * Fix script * BUFG support * debug print if route found with wrong polarity * Some CC_DFF improvements * Create reproducible chip database * Simplify inversion of special signals * Few more DFF features * Add forgotten virtual port renames * Handle muxes with constant inputs * Allow inversion for muxes * cleanup * DFF input can be constant * init DFF only when needed * cleanup * Add basic PLL support * Add some timings * Add USR_RSTN support * Display few more primitives * Use pass trough signals to validate architecture data * Use extra tile information from chip database * Updates needed for a build system changes * Implement SB_DRIVE support * Properly named configuration bits * autogenerated constids.inc * small fix * Initial code for CPE halfs * Some cleanup * make sure FFs are compatible * reverted due to db change * Merge DFF where applicable * memory allocation issue * fix * better MX2 * ram_i handling * Cleanup MX4 * Support latches * compare L_D flag as well * Move virtual pips * Naive addf pack * carry chains grouping * Keep chip database reproducible * split addf vectors * Block CPEs when GPIO is used * Prepare placement code * RAM_I/RAM_O rewrite * fix ram_i/o index * Display RAM and add new primitives * PLL wip code * CC_PLL_ADV packing * PLL handling cleanup * Add PLL comments * Keep only high fan-out BUFG * Add skeleton for tests * Utilize move_ram_o * GPIO wip * GPIO wip * PLL fixes * cleanup * FF_OBF support * Handle FF_IBF * Make SLEW FAST if not defined as in latest p_r * Make sure FF_OBF only driving GPIO * Moved pll calc into separate file * IDDR handling and started ODDR * Route DDR input for CC_ODDR * Notify error in case ODDR or IDDR are used but not with I/O pin * cleanup for CC_USR_RSTN * Extract proper RAM location for bitstream * Code cleanup * Allow auto place of pads * Use clock source flag * Configure GPIO clock signals * Handle conflicting clk * Use BUGF in proper order * Connected CLK, works without but good for debugging * CC_CFG_CTRL placement * Group RAM data 40 bytes per row * Write BRAM content * RAM wip * Use relative constraints from chipdb * fix broken build * Memory wip * Handle custom clock for memories * Support FIFO * optimize move_ram_io * Fix SR signal handling acorrding to findings * set placer beta * Pre place what we can * Revert "debug print if route found with wrong polarity" This reverts commit cf9ded2f183db0f4e85da454e5d9f2a4da3f5cfe. * Revert "Constrain routes to have correct inversion state" This reverts commit 795c284d4856ff17e37d64f013775e86f1bed803. * Remove virtual pips * Implement post processing inversion * ADDF add ability to route additional CO * Merge two ADDFs in one CPE * Added TODO * clangformat * Cleanup * Add serdes handling in config file * Cleanup * Cleanup * Cleanup * Fix in PLL handling * Fixed ADDF edge case * No need for this * Fix latch * Sanity checks * Support CC_BRAM_20K merge * Start creating testing environment * LVDS fixes * Add connection helper * Cleanup * Fix tabs * Formatting fix * Remove optimization tests for now * remove read_bitstream * removed .c_str() * Removed config parsing * using snake_case * Use bool_or_default where applicable * refactored bitstream write code * Add allow-unconstrained option * Update DFF related messages * Add clock constraint propagation --------- Co-authored-by: Lofty <dan.ravensloft@gmail.com>
2025-04-22 16:41:01 +02:00
X(REGFILE_DO_O)
X(REGFILE_RDY_O)
// primitive CC_CFG_CTRL
X(CC_CFG_CTRL)
X(DATA)
//X(CLK)
//X(EN)
X(RECFG)
X(VALID)
// primitive CC_USR_RSTN
X(CC_USR_RSTN)
X(USR_RSTN)
Use improved CPE model (#1503) * CPE mapping improvements * Use CP_OUT for adders * Fixes * Small fixes * Cleanups * Cleanup * Cleanups * Fixes * Fixes * Optimize * Cleanup * clangformat * Cleanup * Cleanup * Bump required version of database * Cleanup * Resolve name conflicts * Fix signal routing * Make CPE_LATCH separate * Add more timings models, need updated values * Fixed warning * multiplier support from lofty/gatemate-mult * explicitly zero some params in B passthrough * comment the relevant CPE inputs in check_multipliers * Rename some of bels * remove _lower from name * refactor multiplier checking * Revert "remove _lower from name" This reverts commit daa1041bdf855b664c8f6462e1ed994459239b9c. * Fixe net name to be unique * Make sure we at least generate bitstream with all info * Simplify zero * Bounded cell type in gui * typo fix * Remove A passthrough inversion option * Clean up CarryGenCell config * Update a passthru to use new primitives * Cleanup for adders * Clean up MsbRoutingCell * Cleanup * Refactor A connection code * Make it more as in PR #1513 * Added cplines to bpassthru and fixed constant driver for A * Add parts * Added comp out connections * clangformat * clangformat * Clean up B passthrough connections * wire up a bunch of intermediate signals * Bit of cleanup * handing of C_EN_IN * C_EN_CIN fixes * connect f_route to its lines * fix cite for FRoutingCell * fixup, oops * connect multfab to its lines * Commented line * Connect CPOUTs * Handle C_I params * connect CINY1 for CarryGenCell * fix carry gen CINX * Update L2T4 model * Updates for ADDCIN * clangformat * fix some issues with multfab and f_route * look at C_I when doing inversion * Only set some C_I signals when used * Fix one more place * do not use cplines so we can merge in one cell * Cover cases that could be optimized out * clangformat * Cleanups * Disable multiplier usage for now --------- Co-authored-by: Lofty <dan.ravensloft@gmail.com>
2025-07-07 10:14:48 +02:00
// hardware primitive CPE_LT_U
X(CPE_LT_U)
// CPE_LT_U pins
Gatemate FPGA initial support (#1473) * Initial code for GateMate * Initial work on forming bitstream * Add CCF parsing * Use CCF to set IO location * Propagate errors * Restructure code * Add support for reading from config * Start adding infrastructure for reading bitstream * Fix script * GPIO initial work * Add IN1->RAM_O2 propagation * Fixed typo * Cleanup * More parameter checks * Add LVDS support * Cleanup * Keep just used connections for now * Naive lut tree CPE pack * Naive pack CC_DFF * pack DFF fixes * Handle MUX flags * Fix DFF pack * Prevent pass trough issues * Cleanup * Use device wrapper class * Update due to API changes * Use pin connection aliases * Start work on BUFG support * Fix CC_L2T5 pack * Add CPE input inverters * Constrain routes to have correct inversion state * Add clock inversion pip * Added MX2 and MX4 support * Fix script * BUFG support * debug print if route found with wrong polarity * Some CC_DFF improvements * Create reproducible chip database * Simplify inversion of special signals * Few more DFF features * Add forgotten virtual port renames * Handle muxes with constant inputs * Allow inversion for muxes * cleanup * DFF input can be constant * init DFF only when needed * cleanup * Add basic PLL support * Add some timings * Add USR_RSTN support * Display few more primitives * Use pass trough signals to validate architecture data * Use extra tile information from chip database * Updates needed for a build system changes * Implement SB_DRIVE support * Properly named configuration bits * autogenerated constids.inc * small fix * Initial code for CPE halfs * Some cleanup * make sure FFs are compatible * reverted due to db change * Merge DFF where applicable * memory allocation issue * fix * better MX2 * ram_i handling * Cleanup MX4 * Support latches * compare L_D flag as well * Move virtual pips * Naive addf pack * carry chains grouping * Keep chip database reproducible * split addf vectors * Block CPEs when GPIO is used * Prepare placement code * RAM_I/RAM_O rewrite * fix ram_i/o index * Display RAM and add new primitives * PLL wip code * CC_PLL_ADV packing * PLL handling cleanup * Add PLL comments * Keep only high fan-out BUFG * Add skeleton for tests * Utilize move_ram_o * GPIO wip * GPIO wip * PLL fixes * cleanup * FF_OBF support * Handle FF_IBF * Make SLEW FAST if not defined as in latest p_r * Make sure FF_OBF only driving GPIO * Moved pll calc into separate file * IDDR handling and started ODDR * Route DDR input for CC_ODDR * Notify error in case ODDR or IDDR are used but not with I/O pin * cleanup for CC_USR_RSTN * Extract proper RAM location for bitstream * Code cleanup * Allow auto place of pads * Use clock source flag * Configure GPIO clock signals * Handle conflicting clk * Use BUGF in proper order * Connected CLK, works without but good for debugging * CC_CFG_CTRL placement * Group RAM data 40 bytes per row * Write BRAM content * RAM wip * Use relative constraints from chipdb * fix broken build * Memory wip * Handle custom clock for memories * Support FIFO * optimize move_ram_io * Fix SR signal handling acorrding to findings * set placer beta * Pre place what we can * Revert "debug print if route found with wrong polarity" This reverts commit cf9ded2f183db0f4e85da454e5d9f2a4da3f5cfe. * Revert "Constrain routes to have correct inversion state" This reverts commit 795c284d4856ff17e37d64f013775e86f1bed803. * Remove virtual pips * Implement post processing inversion * ADDF add ability to route additional CO * Merge two ADDFs in one CPE * Added TODO * clangformat * Cleanup * Add serdes handling in config file * Cleanup * Cleanup * Cleanup * Fix in PLL handling * Fixed ADDF edge case * No need for this * Fix latch * Sanity checks * Support CC_BRAM_20K merge * Start creating testing environment * LVDS fixes * Add connection helper * Cleanup * Fix tabs * Formatting fix * Remove optimization tests for now * remove read_bitstream * removed .c_str() * Removed config parsing * using snake_case * Use bool_or_default where applicable * refactored bitstream write code * Add allow-unconstrained option * Update DFF related messages * Add clock constraint propagation --------- Co-authored-by: Lofty <dan.ravensloft@gmail.com>
2025-04-22 16:41:01 +02:00
X(IN1)
X(IN2)
X(IN3)
X(IN4)
Use improved CPE model (#1503) * CPE mapping improvements * Use CP_OUT for adders * Fixes * Small fixes * Cleanups * Cleanup * Cleanups * Fixes * Fixes * Optimize * Cleanup * clangformat * Cleanup * Cleanup * Bump required version of database * Cleanup * Resolve name conflicts * Fix signal routing * Make CPE_LATCH separate * Add more timings models, need updated values * Fixed warning * multiplier support from lofty/gatemate-mult * explicitly zero some params in B passthrough * comment the relevant CPE inputs in check_multipliers * Rename some of bels * remove _lower from name * refactor multiplier checking * Revert "remove _lower from name" This reverts commit daa1041bdf855b664c8f6462e1ed994459239b9c. * Fixe net name to be unique * Make sure we at least generate bitstream with all info * Simplify zero * Bounded cell type in gui * typo fix * Remove A passthrough inversion option * Clean up CarryGenCell config * Update a passthru to use new primitives * Cleanup for adders * Clean up MsbRoutingCell * Cleanup * Refactor A connection code * Make it more as in PR #1513 * Added cplines to bpassthru and fixed constant driver for A * Add parts * Added comp out connections * clangformat * clangformat * Clean up B passthrough connections * wire up a bunch of intermediate signals * Bit of cleanup * handing of C_EN_IN * C_EN_CIN fixes * connect f_route to its lines * fix cite for FRoutingCell * fixup, oops * connect multfab to its lines * Commented line * Connect CPOUTs * Handle C_I params * connect CINY1 for CarryGenCell * fix carry gen CINX * Update L2T4 model * Updates for ADDCIN * clangformat * fix some issues with multfab and f_route * look at C_I when doing inversion * Only set some C_I signals when used * Fix one more place * do not use cplines so we can merge in one cell * Cover cases that could be optimized out * clangformat * Cleanups * Disable multiplier usage for now --------- Co-authored-by: Lofty <dan.ravensloft@gmail.com>
2025-07-07 10:14:48 +02:00
X(OUT)
X(CPOUT)
X(PINY1)
X(CINX)
// hardware primitive CPE_FF_U
X(CPE_FF_U)
// CPE_FF_U pins
X(DIN)
Gatemate FPGA initial support (#1473) * Initial code for GateMate * Initial work on forming bitstream * Add CCF parsing * Use CCF to set IO location * Propagate errors * Restructure code * Add support for reading from config * Start adding infrastructure for reading bitstream * Fix script * GPIO initial work * Add IN1->RAM_O2 propagation * Fixed typo * Cleanup * More parameter checks * Add LVDS support * Cleanup * Keep just used connections for now * Naive lut tree CPE pack * Naive pack CC_DFF * pack DFF fixes * Handle MUX flags * Fix DFF pack * Prevent pass trough issues * Cleanup * Use device wrapper class * Update due to API changes * Use pin connection aliases * Start work on BUFG support * Fix CC_L2T5 pack * Add CPE input inverters * Constrain routes to have correct inversion state * Add clock inversion pip * Added MX2 and MX4 support * Fix script * BUFG support * debug print if route found with wrong polarity * Some CC_DFF improvements * Create reproducible chip database * Simplify inversion of special signals * Few more DFF features * Add forgotten virtual port renames * Handle muxes with constant inputs * Allow inversion for muxes * cleanup * DFF input can be constant * init DFF only when needed * cleanup * Add basic PLL support * Add some timings * Add USR_RSTN support * Display few more primitives * Use pass trough signals to validate architecture data * Use extra tile information from chip database * Updates needed for a build system changes * Implement SB_DRIVE support * Properly named configuration bits * autogenerated constids.inc * small fix * Initial code for CPE halfs * Some cleanup * make sure FFs are compatible * reverted due to db change * Merge DFF where applicable * memory allocation issue * fix * better MX2 * ram_i handling * Cleanup MX4 * Support latches * compare L_D flag as well * Move virtual pips * Naive addf pack * carry chains grouping * Keep chip database reproducible * split addf vectors * Block CPEs when GPIO is used * Prepare placement code * RAM_I/RAM_O rewrite * fix ram_i/o index * Display RAM and add new primitives * PLL wip code * CC_PLL_ADV packing * PLL handling cleanup * Add PLL comments * Keep only high fan-out BUFG * Add skeleton for tests * Utilize move_ram_o * GPIO wip * GPIO wip * PLL fixes * cleanup * FF_OBF support * Handle FF_IBF * Make SLEW FAST if not defined as in latest p_r * Make sure FF_OBF only driving GPIO * Moved pll calc into separate file * IDDR handling and started ODDR * Route DDR input for CC_ODDR * Notify error in case ODDR or IDDR are used but not with I/O pin * cleanup for CC_USR_RSTN * Extract proper RAM location for bitstream * Code cleanup * Allow auto place of pads * Use clock source flag * Configure GPIO clock signals * Handle conflicting clk * Use BUGF in proper order * Connected CLK, works without but good for debugging * CC_CFG_CTRL placement * Group RAM data 40 bytes per row * Write BRAM content * RAM wip * Use relative constraints from chipdb * fix broken build * Memory wip * Handle custom clock for memories * Support FIFO * optimize move_ram_io * Fix SR signal handling acorrding to findings * set placer beta * Pre place what we can * Revert "debug print if route found with wrong polarity" This reverts commit cf9ded2f183db0f4e85da454e5d9f2a4da3f5cfe. * Revert "Constrain routes to have correct inversion state" This reverts commit 795c284d4856ff17e37d64f013775e86f1bed803. * Remove virtual pips * Implement post processing inversion * ADDF add ability to route additional CO * Merge two ADDFs in one CPE * Added TODO * clangformat * Cleanup * Add serdes handling in config file * Cleanup * Cleanup * Cleanup * Fix in PLL handling * Fixed ADDF edge case * No need for this * Fix latch * Sanity checks * Support CC_BRAM_20K merge * Start creating testing environment * LVDS fixes * Add connection helper * Cleanup * Fix tabs * Formatting fix * Remove optimization tests for now * remove read_bitstream * removed .c_str() * Removed config parsing * using snake_case * Use bool_or_default where applicable * refactored bitstream write code * Add allow-unconstrained option * Update DFF related messages * Add clock constraint propagation --------- Co-authored-by: Lofty <dan.ravensloft@gmail.com>
2025-04-22 16:41:01 +02:00
//X(CLK)
//X(EN)
//X(SR)
Use improved CPE model (#1503) * CPE mapping improvements * Use CP_OUT for adders * Fixes * Small fixes * Cleanups * Cleanup * Cleanups * Fixes * Fixes * Optimize * Cleanup * clangformat * Cleanup * Cleanup * Bump required version of database * Cleanup * Resolve name conflicts * Fix signal routing * Make CPE_LATCH separate * Add more timings models, need updated values * Fixed warning * multiplier support from lofty/gatemate-mult * explicitly zero some params in B passthrough * comment the relevant CPE inputs in check_multipliers * Rename some of bels * remove _lower from name * refactor multiplier checking * Revert "remove _lower from name" This reverts commit daa1041bdf855b664c8f6462e1ed994459239b9c. * Fixe net name to be unique * Make sure we at least generate bitstream with all info * Simplify zero * Bounded cell type in gui * typo fix * Remove A passthrough inversion option * Clean up CarryGenCell config * Update a passthru to use new primitives * Cleanup for adders * Clean up MsbRoutingCell * Cleanup * Refactor A connection code * Make it more as in PR #1513 * Added cplines to bpassthru and fixed constant driver for A * Add parts * Added comp out connections * clangformat * clangformat * Clean up B passthrough connections * wire up a bunch of intermediate signals * Bit of cleanup * handing of C_EN_IN * C_EN_CIN fixes * connect f_route to its lines * fix cite for FRoutingCell * fixup, oops * connect multfab to its lines * Commented line * Connect CPOUTs * Handle C_I params * connect CINY1 for CarryGenCell * fix carry gen CINX * Update L2T4 model * Updates for ADDCIN * clangformat * fix some issues with multfab and f_route * look at C_I when doing inversion * Only set some C_I signals when used * Fix one more place * do not use cplines so we can merge in one cell * Cover cases that could be optimized out * clangformat * Cleanups * Disable multiplier usage for now --------- Co-authored-by: Lofty <dan.ravensloft@gmail.com>
2025-07-07 10:14:48 +02:00
X(DOUT)
// hardware primitive CPE_RAMIO_U
X(CPE_RAMIO_U)
// CPE_RAMIO_U pins
X(RAM_I)
//X(I)
//X(OUT)
Gatemate FPGA initial support (#1473) * Initial code for GateMate * Initial work on forming bitstream * Add CCF parsing * Use CCF to set IO location * Propagate errors * Restructure code * Add support for reading from config * Start adding infrastructure for reading bitstream * Fix script * GPIO initial work * Add IN1->RAM_O2 propagation * Fixed typo * Cleanup * More parameter checks * Add LVDS support * Cleanup * Keep just used connections for now * Naive lut tree CPE pack * Naive pack CC_DFF * pack DFF fixes * Handle MUX flags * Fix DFF pack * Prevent pass trough issues * Cleanup * Use device wrapper class * Update due to API changes * Use pin connection aliases * Start work on BUFG support * Fix CC_L2T5 pack * Add CPE input inverters * Constrain routes to have correct inversion state * Add clock inversion pip * Added MX2 and MX4 support * Fix script * BUFG support * debug print if route found with wrong polarity * Some CC_DFF improvements * Create reproducible chip database * Simplify inversion of special signals * Few more DFF features * Add forgotten virtual port renames * Handle muxes with constant inputs * Allow inversion for muxes * cleanup * DFF input can be constant * init DFF only when needed * cleanup * Add basic PLL support * Add some timings * Add USR_RSTN support * Display few more primitives * Use pass trough signals to validate architecture data * Use extra tile information from chip database * Updates needed for a build system changes * Implement SB_DRIVE support * Properly named configuration bits * autogenerated constids.inc * small fix * Initial code for CPE halfs * Some cleanup * make sure FFs are compatible * reverted due to db change * Merge DFF where applicable * memory allocation issue * fix * better MX2 * ram_i handling * Cleanup MX4 * Support latches * compare L_D flag as well * Move virtual pips * Naive addf pack * carry chains grouping * Keep chip database reproducible * split addf vectors * Block CPEs when GPIO is used * Prepare placement code * RAM_I/RAM_O rewrite * fix ram_i/o index * Display RAM and add new primitives * PLL wip code * CC_PLL_ADV packing * PLL handling cleanup * Add PLL comments * Keep only high fan-out BUFG * Add skeleton for tests * Utilize move_ram_o * GPIO wip * GPIO wip * PLL fixes * cleanup * FF_OBF support * Handle FF_IBF * Make SLEW FAST if not defined as in latest p_r * Make sure FF_OBF only driving GPIO * Moved pll calc into separate file * IDDR handling and started ODDR * Route DDR input for CC_ODDR * Notify error in case ODDR or IDDR are used but not with I/O pin * cleanup for CC_USR_RSTN * Extract proper RAM location for bitstream * Code cleanup * Allow auto place of pads * Use clock source flag * Configure GPIO clock signals * Handle conflicting clk * Use BUGF in proper order * Connected CLK, works without but good for debugging * CC_CFG_CTRL placement * Group RAM data 40 bytes per row * Write BRAM content * RAM wip * Use relative constraints from chipdb * fix broken build * Memory wip * Handle custom clock for memories * Support FIFO * optimize move_ram_io * Fix SR signal handling acorrding to findings * set placer beta * Pre place what we can * Revert "debug print if route found with wrong polarity" This reverts commit cf9ded2f183db0f4e85da454e5d9f2a4da3f5cfe. * Revert "Constrain routes to have correct inversion state" This reverts commit 795c284d4856ff17e37d64f013775e86f1bed803. * Remove virtual pips * Implement post processing inversion * ADDF add ability to route additional CO * Merge two ADDFs in one CPE * Added TODO * clangformat * Cleanup * Add serdes handling in config file * Cleanup * Cleanup * Cleanup * Fix in PLL handling * Fixed ADDF edge case * No need for this * Fix latch * Sanity checks * Support CC_BRAM_20K merge * Start creating testing environment * LVDS fixes * Add connection helper * Cleanup * Fix tabs * Formatting fix * Remove optimization tests for now * remove read_bitstream * removed .c_str() * Removed config parsing * using snake_case * Use bool_or_default where applicable * refactored bitstream write code * Add allow-unconstrained option * Update DFF related messages * Add clock constraint propagation --------- Co-authored-by: Lofty <dan.ravensloft@gmail.com>
2025-04-22 16:41:01 +02:00
X(RAM_O)
Use improved CPE model (#1503) * CPE mapping improvements * Use CP_OUT for adders * Fixes * Small fixes * Cleanups * Cleanup * Cleanups * Fixes * Fixes * Optimize * Cleanup * clangformat * Cleanup * Cleanup * Bump required version of database * Cleanup * Resolve name conflicts * Fix signal routing * Make CPE_LATCH separate * Add more timings models, need updated values * Fixed warning * multiplier support from lofty/gatemate-mult * explicitly zero some params in B passthrough * comment the relevant CPE inputs in check_multipliers * Rename some of bels * remove _lower from name * refactor multiplier checking * Revert "remove _lower from name" This reverts commit daa1041bdf855b664c8f6462e1ed994459239b9c. * Fixe net name to be unique * Make sure we at least generate bitstream with all info * Simplify zero * Bounded cell type in gui * typo fix * Remove A passthrough inversion option * Clean up CarryGenCell config * Update a passthru to use new primitives * Cleanup for adders * Clean up MsbRoutingCell * Cleanup * Refactor A connection code * Make it more as in PR #1513 * Added cplines to bpassthru and fixed constant driver for A * Add parts * Added comp out connections * clangformat * clangformat * Clean up B passthrough connections * wire up a bunch of intermediate signals * Bit of cleanup * handing of C_EN_IN * C_EN_CIN fixes * connect f_route to its lines * fix cite for FRoutingCell * fixup, oops * connect multfab to its lines * Commented line * Connect CPOUTs * Handle C_I params * connect CINY1 for CarryGenCell * fix carry gen CINX * Update L2T4 model * Updates for ADDCIN * clangformat * fix some issues with multfab and f_route * look at C_I when doing inversion * Only set some C_I signals when used * Fix one more place * do not use cplines so we can merge in one cell * Cover cases that could be optimized out * clangformat * Cleanups * Disable multiplier usage for now --------- Co-authored-by: Lofty <dan.ravensloft@gmail.com>
2025-07-07 10:14:48 +02:00
// hardware primitive CPE_LT_L
X(CPE_LT_L)
// CPE_LT_L pins
Gatemate FPGA initial support (#1473) * Initial code for GateMate * Initial work on forming bitstream * Add CCF parsing * Use CCF to set IO location * Propagate errors * Restructure code * Add support for reading from config * Start adding infrastructure for reading bitstream * Fix script * GPIO initial work * Add IN1->RAM_O2 propagation * Fixed typo * Cleanup * More parameter checks * Add LVDS support * Cleanup * Keep just used connections for now * Naive lut tree CPE pack * Naive pack CC_DFF * pack DFF fixes * Handle MUX flags * Fix DFF pack * Prevent pass trough issues * Cleanup * Use device wrapper class * Update due to API changes * Use pin connection aliases * Start work on BUFG support * Fix CC_L2T5 pack * Add CPE input inverters * Constrain routes to have correct inversion state * Add clock inversion pip * Added MX2 and MX4 support * Fix script * BUFG support * debug print if route found with wrong polarity * Some CC_DFF improvements * Create reproducible chip database * Simplify inversion of special signals * Few more DFF features * Add forgotten virtual port renames * Handle muxes with constant inputs * Allow inversion for muxes * cleanup * DFF input can be constant * init DFF only when needed * cleanup * Add basic PLL support * Add some timings * Add USR_RSTN support * Display few more primitives * Use pass trough signals to validate architecture data * Use extra tile information from chip database * Updates needed for a build system changes * Implement SB_DRIVE support * Properly named configuration bits * autogenerated constids.inc * small fix * Initial code for CPE halfs * Some cleanup * make sure FFs are compatible * reverted due to db change * Merge DFF where applicable * memory allocation issue * fix * better MX2 * ram_i handling * Cleanup MX4 * Support latches * compare L_D flag as well * Move virtual pips * Naive addf pack * carry chains grouping * Keep chip database reproducible * split addf vectors * Block CPEs when GPIO is used * Prepare placement code * RAM_I/RAM_O rewrite * fix ram_i/o index * Display RAM and add new primitives * PLL wip code * CC_PLL_ADV packing * PLL handling cleanup * Add PLL comments * Keep only high fan-out BUFG * Add skeleton for tests * Utilize move_ram_o * GPIO wip * GPIO wip * PLL fixes * cleanup * FF_OBF support * Handle FF_IBF * Make SLEW FAST if not defined as in latest p_r * Make sure FF_OBF only driving GPIO * Moved pll calc into separate file * IDDR handling and started ODDR * Route DDR input for CC_ODDR * Notify error in case ODDR or IDDR are used but not with I/O pin * cleanup for CC_USR_RSTN * Extract proper RAM location for bitstream * Code cleanup * Allow auto place of pads * Use clock source flag * Configure GPIO clock signals * Handle conflicting clk * Use BUGF in proper order * Connected CLK, works without but good for debugging * CC_CFG_CTRL placement * Group RAM data 40 bytes per row * Write BRAM content * RAM wip * Use relative constraints from chipdb * fix broken build * Memory wip * Handle custom clock for memories * Support FIFO * optimize move_ram_io * Fix SR signal handling acorrding to findings * set placer beta * Pre place what we can * Revert "debug print if route found with wrong polarity" This reverts commit cf9ded2f183db0f4e85da454e5d9f2a4da3f5cfe. * Revert "Constrain routes to have correct inversion state" This reverts commit 795c284d4856ff17e37d64f013775e86f1bed803. * Remove virtual pips * Implement post processing inversion * ADDF add ability to route additional CO * Merge two ADDFs in one CPE * Added TODO * clangformat * Cleanup * Add serdes handling in config file * Cleanup * Cleanup * Cleanup * Fix in PLL handling * Fixed ADDF edge case * No need for this * Fix latch * Sanity checks * Support CC_BRAM_20K merge * Start creating testing environment * LVDS fixes * Add connection helper * Cleanup * Fix tabs * Formatting fix * Remove optimization tests for now * remove read_bitstream * removed .c_str() * Removed config parsing * using snake_case * Use bool_or_default where applicable * refactored bitstream write code * Add allow-unconstrained option * Update DFF related messages * Add clock constraint propagation --------- Co-authored-by: Lofty <dan.ravensloft@gmail.com>
2025-04-22 16:41:01 +02:00
//X(IN1)
//X(IN2)
//X(IN3)
//X(IN4)
Use improved CPE model (#1503) * CPE mapping improvements * Use CP_OUT for adders * Fixes * Small fixes * Cleanups * Cleanup * Cleanups * Fixes * Fixes * Optimize * Cleanup * clangformat * Cleanup * Cleanup * Bump required version of database * Cleanup * Resolve name conflicts * Fix signal routing * Make CPE_LATCH separate * Add more timings models, need updated values * Fixed warning * multiplier support from lofty/gatemate-mult * explicitly zero some params in B passthrough * comment the relevant CPE inputs in check_multipliers * Rename some of bels * remove _lower from name * refactor multiplier checking * Revert "remove _lower from name" This reverts commit daa1041bdf855b664c8f6462e1ed994459239b9c. * Fixe net name to be unique * Make sure we at least generate bitstream with all info * Simplify zero * Bounded cell type in gui * typo fix * Remove A passthrough inversion option * Clean up CarryGenCell config * Update a passthru to use new primitives * Cleanup for adders * Clean up MsbRoutingCell * Cleanup * Refactor A connection code * Make it more as in PR #1513 * Added cplines to bpassthru and fixed constant driver for A * Add parts * Added comp out connections * clangformat * clangformat * Clean up B passthrough connections * wire up a bunch of intermediate signals * Bit of cleanup * handing of C_EN_IN * C_EN_CIN fixes * connect f_route to its lines * fix cite for FRoutingCell * fixup, oops * connect multfab to its lines * Commented line * Connect CPOUTs * Handle C_I params * connect CINY1 for CarryGenCell * fix carry gen CINX * Update L2T4 model * Updates for ADDCIN * clangformat * fix some issues with multfab and f_route * look at C_I when doing inversion * Only set some C_I signals when used * Fix one more place * do not use cplines so we can merge in one cell * Cover cases that could be optimized out * clangformat * Cleanups * Disable multiplier usage for now --------- Co-authored-by: Lofty <dan.ravensloft@gmail.com>
2025-07-07 10:14:48 +02:00
X(COMBIN)
Gatemate FPGA initial support (#1473) * Initial code for GateMate * Initial work on forming bitstream * Add CCF parsing * Use CCF to set IO location * Propagate errors * Restructure code * Add support for reading from config * Start adding infrastructure for reading bitstream * Fix script * GPIO initial work * Add IN1->RAM_O2 propagation * Fixed typo * Cleanup * More parameter checks * Add LVDS support * Cleanup * Keep just used connections for now * Naive lut tree CPE pack * Naive pack CC_DFF * pack DFF fixes * Handle MUX flags * Fix DFF pack * Prevent pass trough issues * Cleanup * Use device wrapper class * Update due to API changes * Use pin connection aliases * Start work on BUFG support * Fix CC_L2T5 pack * Add CPE input inverters * Constrain routes to have correct inversion state * Add clock inversion pip * Added MX2 and MX4 support * Fix script * BUFG support * debug print if route found with wrong polarity * Some CC_DFF improvements * Create reproducible chip database * Simplify inversion of special signals * Few more DFF features * Add forgotten virtual port renames * Handle muxes with constant inputs * Allow inversion for muxes * cleanup * DFF input can be constant * init DFF only when needed * cleanup * Add basic PLL support * Add some timings * Add USR_RSTN support * Display few more primitives * Use pass trough signals to validate architecture data * Use extra tile information from chip database * Updates needed for a build system changes * Implement SB_DRIVE support * Properly named configuration bits * autogenerated constids.inc * small fix * Initial code for CPE halfs * Some cleanup * make sure FFs are compatible * reverted due to db change * Merge DFF where applicable * memory allocation issue * fix * better MX2 * ram_i handling * Cleanup MX4 * Support latches * compare L_D flag as well * Move virtual pips * Naive addf pack * carry chains grouping * Keep chip database reproducible * split addf vectors * Block CPEs when GPIO is used * Prepare placement code * RAM_I/RAM_O rewrite * fix ram_i/o index * Display RAM and add new primitives * PLL wip code * CC_PLL_ADV packing * PLL handling cleanup * Add PLL comments * Keep only high fan-out BUFG * Add skeleton for tests * Utilize move_ram_o * GPIO wip * GPIO wip * PLL fixes * cleanup * FF_OBF support * Handle FF_IBF * Make SLEW FAST if not defined as in latest p_r * Make sure FF_OBF only driving GPIO * Moved pll calc into separate file * IDDR handling and started ODDR * Route DDR input for CC_ODDR * Notify error in case ODDR or IDDR are used but not with I/O pin * cleanup for CC_USR_RSTN * Extract proper RAM location for bitstream * Code cleanup * Allow auto place of pads * Use clock source flag * Configure GPIO clock signals * Handle conflicting clk * Use BUGF in proper order * Connected CLK, works without but good for debugging * CC_CFG_CTRL placement * Group RAM data 40 bytes per row * Write BRAM content * RAM wip * Use relative constraints from chipdb * fix broken build * Memory wip * Handle custom clock for memories * Support FIFO * optimize move_ram_io * Fix SR signal handling acorrding to findings * set placer beta * Pre place what we can * Revert "debug print if route found with wrong polarity" This reverts commit cf9ded2f183db0f4e85da454e5d9f2a4da3f5cfe. * Revert "Constrain routes to have correct inversion state" This reverts commit 795c284d4856ff17e37d64f013775e86f1bed803. * Remove virtual pips * Implement post processing inversion * ADDF add ability to route additional CO * Merge two ADDFs in one CPE * Added TODO * clangformat * Cleanup * Add serdes handling in config file * Cleanup * Cleanup * Cleanup * Fix in PLL handling * Fixed ADDF edge case * No need for this * Fix latch * Sanity checks * Support CC_BRAM_20K merge * Start creating testing environment * LVDS fixes * Add connection helper * Cleanup * Fix tabs * Formatting fix * Remove optimization tests for now * remove read_bitstream * removed .c_str() * Removed config parsing * using snake_case * Use bool_or_default where applicable * refactored bitstream write code * Add allow-unconstrained option * Update DFF related messages * Add clock constraint propagation --------- Co-authored-by: Lofty <dan.ravensloft@gmail.com>
2025-04-22 16:41:01 +02:00
//X(OUT)
Use improved CPE model (#1503) * CPE mapping improvements * Use CP_OUT for adders * Fixes * Small fixes * Cleanups * Cleanup * Cleanups * Fixes * Fixes * Optimize * Cleanup * clangformat * Cleanup * Cleanup * Bump required version of database * Cleanup * Resolve name conflicts * Fix signal routing * Make CPE_LATCH separate * Add more timings models, need updated values * Fixed warning * multiplier support from lofty/gatemate-mult * explicitly zero some params in B passthrough * comment the relevant CPE inputs in check_multipliers * Rename some of bels * remove _lower from name * refactor multiplier checking * Revert "remove _lower from name" This reverts commit daa1041bdf855b664c8f6462e1ed994459239b9c. * Fixe net name to be unique * Make sure we at least generate bitstream with all info * Simplify zero * Bounded cell type in gui * typo fix * Remove A passthrough inversion option * Clean up CarryGenCell config * Update a passthru to use new primitives * Cleanup for adders * Clean up MsbRoutingCell * Cleanup * Refactor A connection code * Make it more as in PR #1513 * Added cplines to bpassthru and fixed constant driver for A * Add parts * Added comp out connections * clangformat * clangformat * Clean up B passthrough connections * wire up a bunch of intermediate signals * Bit of cleanup * handing of C_EN_IN * C_EN_CIN fixes * connect f_route to its lines * fix cite for FRoutingCell * fixup, oops * connect multfab to its lines * Commented line * Connect CPOUTs * Handle C_I params * connect CINY1 for CarryGenCell * fix carry gen CINX * Update L2T4 model * Updates for ADDCIN * clangformat * fix some issues with multfab and f_route * look at C_I when doing inversion * Only set some C_I signals when used * Fix one more place * do not use cplines so we can merge in one cell * Cover cases that could be optimized out * clangformat * Cleanups * Disable multiplier usage for now --------- Co-authored-by: Lofty <dan.ravensloft@gmail.com>
2025-07-07 10:14:48 +02:00
//X(CPOUT)
//X(CINX)
Gatemate FPGA initial support (#1473) * Initial code for GateMate * Initial work on forming bitstream * Add CCF parsing * Use CCF to set IO location * Propagate errors * Restructure code * Add support for reading from config * Start adding infrastructure for reading bitstream * Fix script * GPIO initial work * Add IN1->RAM_O2 propagation * Fixed typo * Cleanup * More parameter checks * Add LVDS support * Cleanup * Keep just used connections for now * Naive lut tree CPE pack * Naive pack CC_DFF * pack DFF fixes * Handle MUX flags * Fix DFF pack * Prevent pass trough issues * Cleanup * Use device wrapper class * Update due to API changes * Use pin connection aliases * Start work on BUFG support * Fix CC_L2T5 pack * Add CPE input inverters * Constrain routes to have correct inversion state * Add clock inversion pip * Added MX2 and MX4 support * Fix script * BUFG support * debug print if route found with wrong polarity * Some CC_DFF improvements * Create reproducible chip database * Simplify inversion of special signals * Few more DFF features * Add forgotten virtual port renames * Handle muxes with constant inputs * Allow inversion for muxes * cleanup * DFF input can be constant * init DFF only when needed * cleanup * Add basic PLL support * Add some timings * Add USR_RSTN support * Display few more primitives * Use pass trough signals to validate architecture data * Use extra tile information from chip database * Updates needed for a build system changes * Implement SB_DRIVE support * Properly named configuration bits * autogenerated constids.inc * small fix * Initial code for CPE halfs * Some cleanup * make sure FFs are compatible * reverted due to db change * Merge DFF where applicable * memory allocation issue * fix * better MX2 * ram_i handling * Cleanup MX4 * Support latches * compare L_D flag as well * Move virtual pips * Naive addf pack * carry chains grouping * Keep chip database reproducible * split addf vectors * Block CPEs when GPIO is used * Prepare placement code * RAM_I/RAM_O rewrite * fix ram_i/o index * Display RAM and add new primitives * PLL wip code * CC_PLL_ADV packing * PLL handling cleanup * Add PLL comments * Keep only high fan-out BUFG * Add skeleton for tests * Utilize move_ram_o * GPIO wip * GPIO wip * PLL fixes * cleanup * FF_OBF support * Handle FF_IBF * Make SLEW FAST if not defined as in latest p_r * Make sure FF_OBF only driving GPIO * Moved pll calc into separate file * IDDR handling and started ODDR * Route DDR input for CC_ODDR * Notify error in case ODDR or IDDR are used but not with I/O pin * cleanup for CC_USR_RSTN * Extract proper RAM location for bitstream * Code cleanup * Allow auto place of pads * Use clock source flag * Configure GPIO clock signals * Handle conflicting clk * Use BUGF in proper order * Connected CLK, works without but good for debugging * CC_CFG_CTRL placement * Group RAM data 40 bytes per row * Write BRAM content * RAM wip * Use relative constraints from chipdb * fix broken build * Memory wip * Handle custom clock for memories * Support FIFO * optimize move_ram_io * Fix SR signal handling acorrding to findings * set placer beta * Pre place what we can * Revert "debug print if route found with wrong polarity" This reverts commit cf9ded2f183db0f4e85da454e5d9f2a4da3f5cfe. * Revert "Constrain routes to have correct inversion state" This reverts commit 795c284d4856ff17e37d64f013775e86f1bed803. * Remove virtual pips * Implement post processing inversion * ADDF add ability to route additional CO * Merge two ADDFs in one CPE * Added TODO * clangformat * Cleanup * Add serdes handling in config file * Cleanup * Cleanup * Cleanup * Fix in PLL handling * Fixed ADDF edge case * No need for this * Fix latch * Sanity checks * Support CC_BRAM_20K merge * Start creating testing environment * LVDS fixes * Add connection helper * Cleanup * Fix tabs * Formatting fix * Remove optimization tests for now * remove read_bitstream * removed .c_str() * Removed config parsing * using snake_case * Use bool_or_default where applicable * refactored bitstream write code * Add allow-unconstrained option * Update DFF related messages * Add clock constraint propagation --------- Co-authored-by: Lofty <dan.ravensloft@gmail.com>
2025-04-22 16:41:01 +02:00
X(PINX)
X(CINY1)
Use improved CPE model (#1503) * CPE mapping improvements * Use CP_OUT for adders * Fixes * Small fixes * Cleanups * Cleanup * Cleanups * Fixes * Fixes * Optimize * Cleanup * clangformat * Cleanup * Cleanup * Bump required version of database * Cleanup * Resolve name conflicts * Fix signal routing * Make CPE_LATCH separate * Add more timings models, need updated values * Fixed warning * multiplier support from lofty/gatemate-mult * explicitly zero some params in B passthrough * comment the relevant CPE inputs in check_multipliers * Rename some of bels * remove _lower from name * refactor multiplier checking * Revert "remove _lower from name" This reverts commit daa1041bdf855b664c8f6462e1ed994459239b9c. * Fixe net name to be unique * Make sure we at least generate bitstream with all info * Simplify zero * Bounded cell type in gui * typo fix * Remove A passthrough inversion option * Clean up CarryGenCell config * Update a passthru to use new primitives * Cleanup for adders * Clean up MsbRoutingCell * Cleanup * Refactor A connection code * Make it more as in PR #1513 * Added cplines to bpassthru and fixed constant driver for A * Add parts * Added comp out connections * clangformat * clangformat * Clean up B passthrough connections * wire up a bunch of intermediate signals * Bit of cleanup * handing of C_EN_IN * C_EN_CIN fixes * connect f_route to its lines * fix cite for FRoutingCell * fixup, oops * connect multfab to its lines * Commented line * Connect CPOUTs * Handle C_I params * connect CINY1 for CarryGenCell * fix carry gen CINX * Update L2T4 model * Updates for ADDCIN * clangformat * fix some issues with multfab and f_route * look at C_I when doing inversion * Only set some C_I signals when used * Fix one more place * do not use cplines so we can merge in one cell * Cover cases that could be optimized out * clangformat * Cleanups * Disable multiplier usage for now --------- Co-authored-by: Lofty <dan.ravensloft@gmail.com>
2025-07-07 10:14:48 +02:00
//X(PINY1)
Gatemate FPGA initial support (#1473) * Initial code for GateMate * Initial work on forming bitstream * Add CCF parsing * Use CCF to set IO location * Propagate errors * Restructure code * Add support for reading from config * Start adding infrastructure for reading bitstream * Fix script * GPIO initial work * Add IN1->RAM_O2 propagation * Fixed typo * Cleanup * More parameter checks * Add LVDS support * Cleanup * Keep just used connections for now * Naive lut tree CPE pack * Naive pack CC_DFF * pack DFF fixes * Handle MUX flags * Fix DFF pack * Prevent pass trough issues * Cleanup * Use device wrapper class * Update due to API changes * Use pin connection aliases * Start work on BUFG support * Fix CC_L2T5 pack * Add CPE input inverters * Constrain routes to have correct inversion state * Add clock inversion pip * Added MX2 and MX4 support * Fix script * BUFG support * debug print if route found with wrong polarity * Some CC_DFF improvements * Create reproducible chip database * Simplify inversion of special signals * Few more DFF features * Add forgotten virtual port renames * Handle muxes with constant inputs * Allow inversion for muxes * cleanup * DFF input can be constant * init DFF only when needed * cleanup * Add basic PLL support * Add some timings * Add USR_RSTN support * Display few more primitives * Use pass trough signals to validate architecture data * Use extra tile information from chip database * Updates needed for a build system changes * Implement SB_DRIVE support * Properly named configuration bits * autogenerated constids.inc * small fix * Initial code for CPE halfs * Some cleanup * make sure FFs are compatible * reverted due to db change * Merge DFF where applicable * memory allocation issue * fix * better MX2 * ram_i handling * Cleanup MX4 * Support latches * compare L_D flag as well * Move virtual pips * Naive addf pack * carry chains grouping * Keep chip database reproducible * split addf vectors * Block CPEs when GPIO is used * Prepare placement code * RAM_I/RAM_O rewrite * fix ram_i/o index * Display RAM and add new primitives * PLL wip code * CC_PLL_ADV packing * PLL handling cleanup * Add PLL comments * Keep only high fan-out BUFG * Add skeleton for tests * Utilize move_ram_o * GPIO wip * GPIO wip * PLL fixes * cleanup * FF_OBF support * Handle FF_IBF * Make SLEW FAST if not defined as in latest p_r * Make sure FF_OBF only driving GPIO * Moved pll calc into separate file * IDDR handling and started ODDR * Route DDR input for CC_ODDR * Notify error in case ODDR or IDDR are used but not with I/O pin * cleanup for CC_USR_RSTN * Extract proper RAM location for bitstream * Code cleanup * Allow auto place of pads * Use clock source flag * Configure GPIO clock signals * Handle conflicting clk * Use BUGF in proper order * Connected CLK, works without but good for debugging * CC_CFG_CTRL placement * Group RAM data 40 bytes per row * Write BRAM content * RAM wip * Use relative constraints from chipdb * fix broken build * Memory wip * Handle custom clock for memories * Support FIFO * optimize move_ram_io * Fix SR signal handling acorrding to findings * set placer beta * Pre place what we can * Revert "debug print if route found with wrong polarity" This reverts commit cf9ded2f183db0f4e85da454e5d9f2a4da3f5cfe. * Revert "Constrain routes to have correct inversion state" This reverts commit 795c284d4856ff17e37d64f013775e86f1bed803. * Remove virtual pips * Implement post processing inversion * ADDF add ability to route additional CO * Merge two ADDFs in one CPE * Added TODO * clangformat * Cleanup * Add serdes handling in config file * Cleanup * Cleanup * Cleanup * Fix in PLL handling * Fixed ADDF edge case * No need for this * Fix latch * Sanity checks * Support CC_BRAM_20K merge * Start creating testing environment * LVDS fixes * Add connection helper * Cleanup * Fix tabs * Formatting fix * Remove optimization tests for now * remove read_bitstream * removed .c_str() * Removed config parsing * using snake_case * Use bool_or_default where applicable * refactored bitstream write code * Add allow-unconstrained option * Update DFF related messages * Add clock constraint propagation --------- Co-authored-by: Lofty <dan.ravensloft@gmail.com>
2025-04-22 16:41:01 +02:00
X(CINY2)
X(PINY2)
X(COUTX)
X(POUTX)
X(COUTY1)
X(POUTY1)
X(COUTY2)
X(POUTY2)
Use improved CPE model (#1503) * CPE mapping improvements * Use CP_OUT for adders * Fixes * Small fixes * Cleanups * Cleanup * Cleanups * Fixes * Fixes * Optimize * Cleanup * clangformat * Cleanup * Cleanup * Bump required version of database * Cleanup * Resolve name conflicts * Fix signal routing * Make CPE_LATCH separate * Add more timings models, need updated values * Fixed warning * multiplier support from lofty/gatemate-mult * explicitly zero some params in B passthrough * comment the relevant CPE inputs in check_multipliers * Rename some of bels * remove _lower from name * refactor multiplier checking * Revert "remove _lower from name" This reverts commit daa1041bdf855b664c8f6462e1ed994459239b9c. * Fixe net name to be unique * Make sure we at least generate bitstream with all info * Simplify zero * Bounded cell type in gui * typo fix * Remove A passthrough inversion option * Clean up CarryGenCell config * Update a passthru to use new primitives * Cleanup for adders * Clean up MsbRoutingCell * Cleanup * Refactor A connection code * Make it more as in PR #1513 * Added cplines to bpassthru and fixed constant driver for A * Add parts * Added comp out connections * clangformat * clangformat * Clean up B passthrough connections * wire up a bunch of intermediate signals * Bit of cleanup * handing of C_EN_IN * C_EN_CIN fixes * connect f_route to its lines * fix cite for FRoutingCell * fixup, oops * connect multfab to its lines * Commented line * Connect CPOUTs * Handle C_I params * connect CINY1 for CarryGenCell * fix carry gen CINX * Update L2T4 model * Updates for ADDCIN * clangformat * fix some issues with multfab and f_route * look at C_I when doing inversion * Only set some C_I signals when used * Fix one more place * do not use cplines so we can merge in one cell * Cover cases that could be optimized out * clangformat * Cleanups * Disable multiplier usage for now --------- Co-authored-by: Lofty <dan.ravensloft@gmail.com>
2025-07-07 10:14:48 +02:00
// hardware primitive CPE_FF_L
X(CPE_FF_L)
// CPE_FF_L pins
//X(DIN)
//X(CLK)
//X(EN)
//X(SR)
//X(DOUT)
// hardware primitive CPE_RAMIO_L
X(CPE_RAMIO_L)
// CPE_RAMIO_L pins
//X(RAM_I)
//X(I)
//X(OUT)
//X(RAM_O)
// hardware primitive CPE_LT_FULL
X(CPE_LT_FULL)
// CPE_LT_FULL pins
//X(IN1)
//X(IN2)
//X(IN3)
//X(IN4)
X(IN5)
X(IN6)
X(IN7)
X(IN8)
X(OUT1)
X(OUT2)
X(CPOUT1)
X(CPOUT2)
X(MUXOUT)
//X(CINX)
//X(PINX)
//X(CINY1)
//X(PINY1)
//X(CINY2)
//X(PINY2)
//X(COUTX)
//X(POUTX)
//X(COUTY1)
//X(POUTY1)
//X(COUTY2)
//X(POUTY2)
//X(CLK)
//X(EN)
//X(SR)
// hardware primitive CPE_COMP
X(CPE_COMP)
// CPE_COMP pins
X(COMB1)
X(COMB2)
X(COMPOUT)
// hardware primitive CPE_CPLINES
X(CPE_CPLINES)
// CPE_CPLINES pins
//X(OUT1)
//X(OUT2)
//X(COMPOUT)
//X(CINX)
//X(PINX)
//X(CINY1)
//X(PINY1)
//X(CINY2)
//X(PINY2)
//X(COUTX)
//X(POUTX)
//X(COUTY1)
//X(POUTY1)
//X(COUTY2)
//X(POUTY2)
gatemate: add IOSEL as separate primitive (#1533)
2025-08-14 12:20:24 +02:00
// hardware primitive IOSEL
X(IOSEL)
// IOSEL pins
X(GPIO_OUT)
X(GPIO_EN)
X(GPIO_IN)
Gatemate FPGA initial support (#1473) * Initial code for GateMate * Initial work on forming bitstream * Add CCF parsing * Use CCF to set IO location * Propagate errors * Restructure code * Add support for reading from config * Start adding infrastructure for reading bitstream * Fix script * GPIO initial work * Add IN1->RAM_O2 propagation * Fixed typo * Cleanup * More parameter checks * Add LVDS support * Cleanup * Keep just used connections for now * Naive lut tree CPE pack * Naive pack CC_DFF * pack DFF fixes * Handle MUX flags * Fix DFF pack * Prevent pass trough issues * Cleanup * Use device wrapper class * Update due to API changes * Use pin connection aliases * Start work on BUFG support * Fix CC_L2T5 pack * Add CPE input inverters * Constrain routes to have correct inversion state * Add clock inversion pip * Added MX2 and MX4 support * Fix script * BUFG support * debug print if route found with wrong polarity * Some CC_DFF improvements * Create reproducible chip database * Simplify inversion of special signals * Few more DFF features * Add forgotten virtual port renames * Handle muxes with constant inputs * Allow inversion for muxes * cleanup * DFF input can be constant * init DFF only when needed * cleanup * Add basic PLL support * Add some timings * Add USR_RSTN support * Display few more primitives * Use pass trough signals to validate architecture data * Use extra tile information from chip database * Updates needed for a build system changes * Implement SB_DRIVE support * Properly named configuration bits * autogenerated constids.inc * small fix * Initial code for CPE halfs * Some cleanup * make sure FFs are compatible * reverted due to db change * Merge DFF where applicable * memory allocation issue * fix * better MX2 * ram_i handling * Cleanup MX4 * Support latches * compare L_D flag as well * Move virtual pips * Naive addf pack * carry chains grouping * Keep chip database reproducible * split addf vectors * Block CPEs when GPIO is used * Prepare placement code * RAM_I/RAM_O rewrite * fix ram_i/o index * Display RAM and add new primitives * PLL wip code * CC_PLL_ADV packing * PLL handling cleanup * Add PLL comments * Keep only high fan-out BUFG * Add skeleton for tests * Utilize move_ram_o * GPIO wip * GPIO wip * PLL fixes * cleanup * FF_OBF support * Handle FF_IBF * Make SLEW FAST if not defined as in latest p_r * Make sure FF_OBF only driving GPIO * Moved pll calc into separate file * IDDR handling and started ODDR * Route DDR input for CC_ODDR * Notify error in case ODDR or IDDR are used but not with I/O pin * cleanup for CC_USR_RSTN * Extract proper RAM location for bitstream * Code cleanup * Allow auto place of pads * Use clock source flag * Configure GPIO clock signals * Handle conflicting clk * Use BUGF in proper order * Connected CLK, works without but good for debugging * CC_CFG_CTRL placement * Group RAM data 40 bytes per row * Write BRAM content * RAM wip * Use relative constraints from chipdb * fix broken build * Memory wip * Handle custom clock for memories * Support FIFO * optimize move_ram_io * Fix SR signal handling acorrding to findings * set placer beta * Pre place what we can * Revert "debug print if route found with wrong polarity" This reverts commit cf9ded2f183db0f4e85da454e5d9f2a4da3f5cfe. * Revert "Constrain routes to have correct inversion state" This reverts commit 795c284d4856ff17e37d64f013775e86f1bed803. * Remove virtual pips * Implement post processing inversion * ADDF add ability to route additional CO * Merge two ADDFs in one CPE * Added TODO * clangformat * Cleanup * Add serdes handling in config file * Cleanup * Cleanup * Cleanup * Fix in PLL handling * Fixed ADDF edge case * No need for this * Fix latch * Sanity checks * Support CC_BRAM_20K merge * Start creating testing environment * LVDS fixes * Add connection helper * Cleanup * Fix tabs * Formatting fix * Remove optimization tests for now * remove read_bitstream * removed .c_str() * Removed config parsing * using snake_case * Use bool_or_default where applicable * refactored bitstream write code * Add allow-unconstrained option * Update DFF related messages * Add clock constraint propagation --------- Co-authored-by: Lofty <dan.ravensloft@gmail.com>
2025-04-22 16:41:01 +02:00
//X(IN1)
//X(IN2)
Use improved CPE model (#1503) * CPE mapping improvements * Use CP_OUT for adders * Fixes * Small fixes * Cleanups * Cleanup * Cleanups * Fixes * Fixes * Optimize * Cleanup * clangformat * Cleanup * Cleanup * Bump required version of database * Cleanup * Resolve name conflicts * Fix signal routing * Make CPE_LATCH separate * Add more timings models, need updated values * Fixed warning * multiplier support from lofty/gatemate-mult * explicitly zero some params in B passthrough * comment the relevant CPE inputs in check_multipliers * Rename some of bels * remove _lower from name * refactor multiplier checking * Revert "remove _lower from name" This reverts commit daa1041bdf855b664c8f6462e1ed994459239b9c. * Fixe net name to be unique * Make sure we at least generate bitstream with all info * Simplify zero * Bounded cell type in gui * typo fix * Remove A passthrough inversion option * Clean up CarryGenCell config * Update a passthru to use new primitives * Cleanup for adders * Clean up MsbRoutingCell * Cleanup * Refactor A connection code * Make it more as in PR #1513 * Added cplines to bpassthru and fixed constant driver for A * Add parts * Added comp out connections * clangformat * clangformat * Clean up B passthrough connections * wire up a bunch of intermediate signals * Bit of cleanup * handing of C_EN_IN * C_EN_CIN fixes * connect f_route to its lines * fix cite for FRoutingCell * fixup, oops * connect multfab to its lines * Commented line * Connect CPOUTs * Handle C_I params * connect CINY1 for CarryGenCell * fix carry gen CINX * Update L2T4 model * Updates for ADDCIN * clangformat * fix some issues with multfab and f_route * look at C_I when doing inversion * Only set some C_I signals when used * Fix one more place * do not use cplines so we can merge in one cell * Cover cases that could be optimized out * clangformat * Cleanups * Disable multiplier usage for now --------- Co-authored-by: Lofty <dan.ravensloft@gmail.com>
2025-07-07 10:14:48 +02:00
//X(OUT1)
//X(OUT2)
Gatemate FPGA initial support (#1473) * Initial code for GateMate * Initial work on forming bitstream * Add CCF parsing * Use CCF to set IO location * Propagate errors * Restructure code * Add support for reading from config * Start adding infrastructure for reading bitstream * Fix script * GPIO initial work * Add IN1->RAM_O2 propagation * Fixed typo * Cleanup * More parameter checks * Add LVDS support * Cleanup * Keep just used connections for now * Naive lut tree CPE pack * Naive pack CC_DFF * pack DFF fixes * Handle MUX flags * Fix DFF pack * Prevent pass trough issues * Cleanup * Use device wrapper class * Update due to API changes * Use pin connection aliases * Start work on BUFG support * Fix CC_L2T5 pack * Add CPE input inverters * Constrain routes to have correct inversion state * Add clock inversion pip * Added MX2 and MX4 support * Fix script * BUFG support * debug print if route found with wrong polarity * Some CC_DFF improvements * Create reproducible chip database * Simplify inversion of special signals * Few more DFF features * Add forgotten virtual port renames * Handle muxes with constant inputs * Allow inversion for muxes * cleanup * DFF input can be constant * init DFF only when needed * cleanup * Add basic PLL support * Add some timings * Add USR_RSTN support * Display few more primitives * Use pass trough signals to validate architecture data * Use extra tile information from chip database * Updates needed for a build system changes * Implement SB_DRIVE support * Properly named configuration bits * autogenerated constids.inc * small fix * Initial code for CPE halfs * Some cleanup * make sure FFs are compatible * reverted due to db change * Merge DFF where applicable * memory allocation issue * fix * better MX2 * ram_i handling * Cleanup MX4 * Support latches * compare L_D flag as well * Move virtual pips * Naive addf pack * carry chains grouping * Keep chip database reproducible * split addf vectors * Block CPEs when GPIO is used * Prepare placement code * RAM_I/RAM_O rewrite * fix ram_i/o index * Display RAM and add new primitives * PLL wip code * CC_PLL_ADV packing * PLL handling cleanup * Add PLL comments * Keep only high fan-out BUFG * Add skeleton for tests * Utilize move_ram_o * GPIO wip * GPIO wip * PLL fixes * cleanup * FF_OBF support * Handle FF_IBF * Make SLEW FAST if not defined as in latest p_r * Make sure FF_OBF only driving GPIO * Moved pll calc into separate file * IDDR handling and started ODDR * Route DDR input for CC_ODDR * Notify error in case ODDR or IDDR are used but not with I/O pin * cleanup for CC_USR_RSTN * Extract proper RAM location for bitstream * Code cleanup * Allow auto place of pads * Use clock source flag * Configure GPIO clock signals * Handle conflicting clk * Use BUGF in proper order * Connected CLK, works without but good for debugging * CC_CFG_CTRL placement * Group RAM data 40 bytes per row * Write BRAM content * RAM wip * Use relative constraints from chipdb * fix broken build * Memory wip * Handle custom clock for memories * Support FIFO * optimize move_ram_io * Fix SR signal handling acorrding to findings * set placer beta * Pre place what we can * Revert "debug print if route found with wrong polarity" This reverts commit cf9ded2f183db0f4e85da454e5d9f2a4da3f5cfe. * Revert "Constrain routes to have correct inversion state" This reverts commit 795c284d4856ff17e37d64f013775e86f1bed803. * Remove virtual pips * Implement post processing inversion * ADDF add ability to route additional CO * Merge two ADDFs in one CPE * Added TODO * clangformat * Cleanup * Add serdes handling in config file * Cleanup * Cleanup * Cleanup * Fix in PLL handling * Fixed ADDF edge case * No need for this * Fix latch * Sanity checks * Support CC_BRAM_20K merge * Start creating testing environment * LVDS fixes * Add connection helper * Cleanup * Fix tabs * Formatting fix * Remove optimization tests for now * remove read_bitstream * removed .c_str() * Removed config parsing * using snake_case * Use bool_or_default where applicable * refactored bitstream write code * Add allow-unconstrained option * Update DFF related messages * Add clock constraint propagation --------- Co-authored-by: Lofty <dan.ravensloft@gmail.com>
2025-04-22 16:41:01 +02:00
X(OUT3)
X(OUT4)
//X(DDR)
X(CLOCK1)
X(CLOCK2)
X(CLOCK3)
X(CLOCK4)
gatemate: add IOSEL as separate primitive (#1533)
2025-08-14 12:20:24 +02:00
// hardware primitive GPIO
X(GPIO)
// GPIO pins
//X(Y)
//X(T)
//X(A)
Gatemate FPGA initial support (#1473) * Initial code for GateMate * Initial work on forming bitstream * Add CCF parsing * Use CCF to set IO location * Propagate errors * Restructure code * Add support for reading from config * Start adding infrastructure for reading bitstream * Fix script * GPIO initial work * Add IN1->RAM_O2 propagation * Fixed typo * Cleanup * More parameter checks * Add LVDS support * Cleanup * Keep just used connections for now * Naive lut tree CPE pack * Naive pack CC_DFF * pack DFF fixes * Handle MUX flags * Fix DFF pack * Prevent pass trough issues * Cleanup * Use device wrapper class * Update due to API changes * Use pin connection aliases * Start work on BUFG support * Fix CC_L2T5 pack * Add CPE input inverters * Constrain routes to have correct inversion state * Add clock inversion pip * Added MX2 and MX4 support * Fix script * BUFG support * debug print if route found with wrong polarity * Some CC_DFF improvements * Create reproducible chip database * Simplify inversion of special signals * Few more DFF features * Add forgotten virtual port renames * Handle muxes with constant inputs * Allow inversion for muxes * cleanup * DFF input can be constant * init DFF only when needed * cleanup * Add basic PLL support * Add some timings * Add USR_RSTN support * Display few more primitives * Use pass trough signals to validate architecture data * Use extra tile information from chip database * Updates needed for a build system changes * Implement SB_DRIVE support * Properly named configuration bits * autogenerated constids.inc * small fix * Initial code for CPE halfs * Some cleanup * make sure FFs are compatible * reverted due to db change * Merge DFF where applicable * memory allocation issue * fix * better MX2 * ram_i handling * Cleanup MX4 * Support latches * compare L_D flag as well * Move virtual pips * Naive addf pack * carry chains grouping * Keep chip database reproducible * split addf vectors * Block CPEs when GPIO is used * Prepare placement code * RAM_I/RAM_O rewrite * fix ram_i/o index * Display RAM and add new primitives * PLL wip code * CC_PLL_ADV packing * PLL handling cleanup * Add PLL comments * Keep only high fan-out BUFG * Add skeleton for tests * Utilize move_ram_o * GPIO wip * GPIO wip * PLL fixes * cleanup * FF_OBF support * Handle FF_IBF * Make SLEW FAST if not defined as in latest p_r * Make sure FF_OBF only driving GPIO * Moved pll calc into separate file * IDDR handling and started ODDR * Route DDR input for CC_ODDR * Notify error in case ODDR or IDDR are used but not with I/O pin * cleanup for CC_USR_RSTN * Extract proper RAM location for bitstream * Code cleanup * Allow auto place of pads * Use clock source flag * Configure GPIO clock signals * Handle conflicting clk * Use BUGF in proper order * Connected CLK, works without but good for debugging * CC_CFG_CTRL placement * Group RAM data 40 bytes per row * Write BRAM content * RAM wip * Use relative constraints from chipdb * fix broken build * Memory wip * Handle custom clock for memories * Support FIFO * optimize move_ram_io * Fix SR signal handling acorrding to findings * set placer beta * Pre place what we can * Revert "debug print if route found with wrong polarity" This reverts commit cf9ded2f183db0f4e85da454e5d9f2a4da3f5cfe. * Revert "Constrain routes to have correct inversion state" This reverts commit 795c284d4856ff17e37d64f013775e86f1bed803. * Remove virtual pips * Implement post processing inversion * ADDF add ability to route additional CO * Merge two ADDFs in one CPE * Added TODO * clangformat * Cleanup * Add serdes handling in config file * Cleanup * Cleanup * Cleanup * Fix in PLL handling * Fixed ADDF edge case * No need for this * Fix latch * Sanity checks * Support CC_BRAM_20K merge * Start creating testing environment * LVDS fixes * Add connection helper * Cleanup * Fix tabs * Formatting fix * Remove optimization tests for now * remove read_bitstream * removed .c_str() * Removed config parsing * using snake_case * Use bool_or_default where applicable * refactored bitstream write code * Add allow-unconstrained option * Update DFF related messages * Add clock constraint propagation --------- Co-authored-by: Lofty <dan.ravensloft@gmail.com>
2025-04-22 16:41:01 +02:00
//X(I)
//X(O)
gatemate: Multi die support and primitives model improvement (#1501) * SER_CLK support * Update constids * wip * CLK_FEEDBACK * Handle SER_CLK and SER_CLK_N * clangformat * Cleanup * Use _ as separator for PLL CFGs * Remove unused clocking cells * Do not use same name for IO models * Fix IDDR merge * Cleanup * Properly handle user global signals * Move signal inversion in bitstream creation * Start adding multi die support * Display die location for pins used * Do not use constant s as locations * Cleanup SB_DRIVE handling * Use DDR locations from chip database * Place only in prefered die for now * Set D2D * Fixed typos
2025-06-18 08:32:57 +02:00
//X(IO)
//X(I_P)
//X(I_N)
//X(O_P)
//X(O_N)
//X(IO_P)
//X(IO_N)
// hardware primitive CLKIN
X(CLKIN)
// CLKIN pins
//X(CLK0)
X(CLK1)
X(CLK2)
X(CLK3)
X(SER_CLK)
X(CLK_REF0)
X(CLK_REF1)
X(CLK_REF2)
X(CLK_REF3)
// hardware primitive GLBOUT
X(GLBOUT)
// GLBOUT pins
X(CLK0_0)
X(CLK90_0)
X(CLK180_0)
X(CLK270_0)
X(CLK_REF_OUT0)
X(USR_GLB0)
X(USR_FB0)
X(CLK_FB0)
X(GLB0)
X(CLK0_1)
X(CLK90_1)
X(CLK180_1)
X(CLK270_1)
X(CLK_REF_OUT1)
X(USR_GLB1)
X(USR_FB1)
X(CLK_FB1)
X(GLB1)
X(CLK0_2)
X(CLK90_2)
X(CLK180_2)
X(CLK270_2)
X(CLK_REF_OUT2)
X(USR_GLB2)
X(USR_FB2)
X(CLK_FB2)
X(GLB2)
X(CLK0_3)
X(CLK90_3)
X(CLK180_3)
X(CLK270_3)
X(CLK_REF_OUT3)
X(USR_GLB3)
X(USR_FB3)
X(CLK_FB3)
X(GLB3)
Gatemate FPGA initial support (#1473) * Initial code for GateMate * Initial work on forming bitstream * Add CCF parsing * Use CCF to set IO location * Propagate errors * Restructure code * Add support for reading from config * Start adding infrastructure for reading bitstream * Fix script * GPIO initial work * Add IN1->RAM_O2 propagation * Fixed typo * Cleanup * More parameter checks * Add LVDS support * Cleanup * Keep just used connections for now * Naive lut tree CPE pack * Naive pack CC_DFF * pack DFF fixes * Handle MUX flags * Fix DFF pack * Prevent pass trough issues * Cleanup * Use device wrapper class * Update due to API changes * Use pin connection aliases * Start work on BUFG support * Fix CC_L2T5 pack * Add CPE input inverters * Constrain routes to have correct inversion state * Add clock inversion pip * Added MX2 and MX4 support * Fix script * BUFG support * debug print if route found with wrong polarity * Some CC_DFF improvements * Create reproducible chip database * Simplify inversion of special signals * Few more DFF features * Add forgotten virtual port renames * Handle muxes with constant inputs * Allow inversion for muxes * cleanup * DFF input can be constant * init DFF only when needed * cleanup * Add basic PLL support * Add some timings * Add USR_RSTN support * Display few more primitives * Use pass trough signals to validate architecture data * Use extra tile information from chip database * Updates needed for a build system changes * Implement SB_DRIVE support * Properly named configuration bits * autogenerated constids.inc * small fix * Initial code for CPE halfs * Some cleanup * make sure FFs are compatible * reverted due to db change * Merge DFF where applicable * memory allocation issue * fix * better MX2 * ram_i handling * Cleanup MX4 * Support latches * compare L_D flag as well * Move virtual pips * Naive addf pack * carry chains grouping * Keep chip database reproducible * split addf vectors * Block CPEs when GPIO is used * Prepare placement code * RAM_I/RAM_O rewrite * fix ram_i/o index * Display RAM and add new primitives * PLL wip code * CC_PLL_ADV packing * PLL handling cleanup * Add PLL comments * Keep only high fan-out BUFG * Add skeleton for tests * Utilize move_ram_o * GPIO wip * GPIO wip * PLL fixes * cleanup * FF_OBF support * Handle FF_IBF * Make SLEW FAST if not defined as in latest p_r * Make sure FF_OBF only driving GPIO * Moved pll calc into separate file * IDDR handling and started ODDR * Route DDR input for CC_ODDR * Notify error in case ODDR or IDDR are used but not with I/O pin * cleanup for CC_USR_RSTN * Extract proper RAM location for bitstream * Code cleanup * Allow auto place of pads * Use clock source flag * Configure GPIO clock signals * Handle conflicting clk * Use BUGF in proper order * Connected CLK, works without but good for debugging * CC_CFG_CTRL placement * Group RAM data 40 bytes per row * Write BRAM content * RAM wip * Use relative constraints from chipdb * fix broken build * Memory wip * Handle custom clock for memories * Support FIFO * optimize move_ram_io * Fix SR signal handling acorrding to findings * set placer beta * Pre place what we can * Revert "debug print if route found with wrong polarity" This reverts commit cf9ded2f183db0f4e85da454e5d9f2a4da3f5cfe. * Revert "Constrain routes to have correct inversion state" This reverts commit 795c284d4856ff17e37d64f013775e86f1bed803. * Remove virtual pips * Implement post processing inversion * ADDF add ability to route additional CO * Merge two ADDFs in one CPE * Added TODO * clangformat * Cleanup * Add serdes handling in config file * Cleanup * Cleanup * Cleanup * Fix in PLL handling * Fixed ADDF edge case * No need for this * Fix latch * Sanity checks * Support CC_BRAM_20K merge * Start creating testing environment * LVDS fixes * Add connection helper * Cleanup * Fix tabs * Formatting fix * Remove optimization tests for now * remove read_bitstream * removed .c_str() * Removed config parsing * using snake_case * Use bool_or_default where applicable * refactored bitstream write code * Add allow-unconstrained option * Update DFF related messages * Add clock constraint propagation --------- Co-authored-by: Lofty <dan.ravensloft@gmail.com>
2025-04-22 16:41:01 +02:00
// hardware primitive PLL
X(PLL)
// PLL pins
//X(CLK_REF)
//X(USR_CLK_REF)
//X(USR_SEL_A_B)
//X(CLK_FEEDBACK)
//X(USR_LOCKED_STDY_RST)
//X(CLK0)
//X(CLK90)
//X(CLK180)
//X(CLK270)
//X(CLK_REF_OUT)
//X(USR_PLL_LOCKED_STDY)
//X(USR_PLL_LOCKED)
// hardware primitive USR_RSTN
//X(USR_RSTN)
// USR_RSTN pins
//X(USR_RSTN)
// hardware primitive CFG_CTRL
X(CFG_CTRL)
// CFG_CTRL pins
//X(DATA[7])
//X(DATA[6])
//X(DATA[5])
//X(DATA[4])
//X(DATA[3])
//X(DATA[2])
//X(DATA[1])
//X(DATA[0])
//X(CLK)
//X(EN)
//X(VALID)
//X(RECFG)
// hardware primitive RAM
X(RAM)
// RAM pins
//X(C_ADDRA[0])
//X(C_ADDRA[1])
//X(C_ADDRA[2])
//X(C_ADDRA[3])
//X(C_ADDRA[4])
//X(C_ADDRA[5])
//X(C_ADDRA[6])
//X(C_ADDRA[7])
//X(C_ADDRB[0])
//X(C_ADDRB[1])
//X(C_ADDRB[2])
//X(C_ADDRB[3])
//X(C_ADDRB[4])
//X(C_ADDRB[5])
//X(C_ADDRB[6])
//X(C_ADDRB[7])
//X(CLKA[0])
//X(CLKA[1])
//X(ENA[0])
//X(ENA[1])
//X(GLWEA[0])
//X(GLWEA[1])
//X(ADDRA0[0])
//X(ADDRA0[1])
//X(ADDRA0[2])
//X(ADDRA0[3])
//X(ADDRA0[4])
//X(ADDRA0[5])
//X(ADDRA0[6])
//X(ADDRA0[7])
//X(ADDRA0[8])
//X(ADDRA0[9])
//X(ADDRA0[10])
//X(ADDRA0[11])
//X(ADDRA0[12])
//X(ADDRA0[13])
//X(ADDRA0[14])
//X(ADDRA0[15])
//X(ADDRA0X[0])
//X(ADDRA0X[1])
//X(ADDRA0X[2])
//X(ADDRA0X[3])
//X(ADDRA0X[4])
//X(ADDRA0X[5])
//X(ADDRA0X[6])
//X(ADDRA0X[7])
//X(ADDRA0X[8])
//X(ADDRA0X[9])
//X(ADDRA0X[10])
//X(ADDRA0X[11])
//X(ADDRA0X[12])
//X(ADDRA0X[13])
//X(ADDRA0X[14])
//X(ADDRA0X[15])
//X(DIA[0])
//X(DIA[1])
//X(DIA[2])
//X(DIA[3])
//X(DIA[4])
//X(DIA[5])
//X(DIA[6])
//X(DIA[7])
//X(DIA[8])
//X(DIA[9])
//X(DIA[10])
//X(DIA[11])
//X(DIA[12])
//X(DIA[13])
//X(DIA[14])
//X(DIA[15])
//X(DIA[16])
//X(DIA[17])
//X(DIA[18])
//X(DIA[19])
//X(WEA[0])
//X(WEA[1])
//X(WEA[2])
//X(WEA[3])
//X(WEA[4])
//X(WEA[5])
//X(WEA[6])
//X(WEA[7])
//X(WEA[8])
//X(WEA[9])
//X(WEA[10])
//X(WEA[11])
//X(WEA[12])
//X(WEA[13])
//X(WEA[14])
//X(WEA[15])
//X(WEA[16])
//X(WEA[17])
//X(WEA[18])
//X(WEA[19])
//X(CLKA[2])
//X(CLKA[3])
//X(ENA[2])
//X(ENA[3])
//X(GLWEA[2])
//X(GLWEA[3])
//X(ADDRA1[0])
//X(ADDRA1[1])
//X(ADDRA1[2])
//X(ADDRA1[3])
//X(ADDRA1[4])
//X(ADDRA1[5])
//X(ADDRA1[6])
//X(ADDRA1[7])
//X(ADDRA1[8])
//X(ADDRA1[9])
//X(ADDRA1[10])
//X(ADDRA1[11])
//X(ADDRA1[12])
//X(ADDRA1[13])
//X(ADDRA1[14])
//X(ADDRA1[15])
//X(ADDRA1X[0])
//X(ADDRA1X[1])
//X(ADDRA1X[2])
//X(ADDRA1X[3])
//X(ADDRA1X[4])
//X(ADDRA1X[5])
//X(ADDRA1X[6])
//X(ADDRA1X[7])
//X(ADDRA1X[8])
//X(ADDRA1X[9])
//X(ADDRA1X[10])
//X(ADDRA1X[11])
//X(ADDRA1X[12])
//X(ADDRA1X[13])
//X(ADDRA1X[14])
//X(ADDRA1X[15])
//X(DIA[20])
//X(DIA[21])
//X(DIA[22])
//X(DIA[23])
//X(DIA[24])
//X(DIA[25])
//X(DIA[26])
//X(DIA[27])
//X(DIA[28])
//X(DIA[29])
//X(DIA[30])
//X(DIA[31])
//X(DIA[32])
//X(DIA[33])
//X(DIA[34])
//X(DIA[35])
//X(DIA[36])
//X(DIA[37])
//X(DIA[38])
//X(DIA[39])
//X(WEA[20])
//X(WEA[21])
//X(WEA[22])
//X(WEA[23])
//X(WEA[24])
//X(WEA[25])
//X(WEA[26])
//X(WEA[27])
//X(WEA[28])
//X(WEA[29])
//X(WEA[30])
//X(WEA[31])
//X(WEA[32])
//X(WEA[33])
//X(WEA[34])
//X(WEA[35])
//X(WEA[36])
//X(WEA[37])
//X(WEA[38])
//X(WEA[39])
//X(CLKB[0])
//X(CLKB[1])
//X(ENB[0])
//X(ENB[1])
//X(GLWEB[0])
//X(GLWEB[1])
//X(ADDRB0[0])
//X(ADDRB0[1])
//X(ADDRB0[2])
//X(ADDRB0[3])
//X(ADDRB0[4])
//X(ADDRB0[5])
//X(ADDRB0[6])
//X(ADDRB0[7])
//X(ADDRB0[8])
//X(ADDRB0[9])
//X(ADDRB0[10])
//X(ADDRB0[11])
//X(ADDRB0[12])
//X(ADDRB0[13])
//X(ADDRB0[14])
//X(ADDRB0[15])
//X(ADDRB0X[0])
//X(ADDRB0X[1])
//X(ADDRB0X[2])
//X(ADDRB0X[3])
//X(ADDRB0X[4])
//X(ADDRB0X[5])
//X(ADDRB0X[6])
//X(ADDRB0X[7])
//X(ADDRB0X[8])
//X(ADDRB0X[9])
//X(ADDRB0X[10])
//X(ADDRB0X[11])
//X(ADDRB0X[12])
//X(ADDRB0X[13])
//X(ADDRB0X[14])
//X(ADDRB0X[15])
//X(DIB[0])
//X(DIB[1])
//X(DIB[2])
//X(DIB[3])
//X(DIB[4])
//X(DIB[5])
//X(DIB[6])
//X(DIB[7])
//X(DIB[8])
//X(DIB[9])
//X(DIB[10])
//X(DIB[11])
//X(DIB[12])
//X(DIB[13])
//X(DIB[14])
//X(DIB[15])
//X(DIB[16])
//X(DIB[17])
//X(DIB[18])
//X(DIB[19])
//X(WEB[0])
//X(WEB[1])
//X(WEB[2])
//X(WEB[3])
//X(WEB[4])
//X(WEB[5])
//X(WEB[6])
//X(WEB[7])
//X(WEB[8])
//X(WEB[9])
//X(WEB[10])
//X(WEB[11])
//X(WEB[12])
//X(WEB[13])
//X(WEB[14])
//X(WEB[15])
//X(WEB[16])
//X(WEB[17])
//X(WEB[18])
//X(WEB[19])
//X(CLKB[2])
//X(CLKB[3])
//X(ENB[2])
//X(ENB[3])
//X(GLWEB[2])
//X(GLWEB[3])
//X(ADDRB1[0])
//X(ADDRB1[1])
//X(ADDRB1[2])
//X(ADDRB1[3])
//X(ADDRB1[4])
//X(ADDRB1[5])
//X(ADDRB1[6])
//X(ADDRB1[7])
//X(ADDRB1[8])
//X(ADDRB1[9])
//X(ADDRB1[10])
//X(ADDRB1[11])
//X(ADDRB1[12])
//X(ADDRB1[13])
//X(ADDRB1[14])
//X(ADDRB1[15])
//X(ADDRB1X[0])
//X(ADDRB1X[1])
//X(ADDRB1X[2])
//X(ADDRB1X[3])
//X(ADDRB1X[4])
//X(ADDRB1X[5])
//X(ADDRB1X[6])
//X(ADDRB1X[7])
//X(ADDRB1X[8])
//X(ADDRB1X[9])
//X(ADDRB1X[10])
//X(ADDRB1X[11])
//X(ADDRB1X[12])
//X(ADDRB1X[13])
//X(ADDRB1X[14])
//X(ADDRB1X[15])
//X(DIB[20])
//X(DIB[21])
//X(DIB[22])
//X(DIB[23])
//X(DIB[24])
//X(DIB[25])
//X(DIB[26])
//X(DIB[27])
//X(DIB[28])
//X(DIB[29])
//X(DIB[30])
//X(DIB[31])
//X(DIB[32])
//X(DIB[33])
//X(DIB[34])
//X(DIB[35])
//X(DIB[36])
//X(DIB[37])
//X(DIB[38])
//X(DIB[39])
//X(WEB[20])
//X(WEB[21])
//X(WEB[22])
//X(WEB[23])
//X(WEB[24])
//X(WEB[25])
//X(WEB[26])
//X(WEB[27])
//X(WEB[28])
//X(WEB[29])
//X(WEB[30])
//X(WEB[31])
//X(WEB[32])
//X(WEB[33])
//X(WEB[34])
//X(WEB[35])
//X(WEB[36])
//X(WEB[37])
//X(WEB[38])
//X(WEB[39])
X(F_RSTN)
//X(DOA[0])
//X(DOAX[0])
//X(DOA[1])
//X(DOAX[1])
//X(DOA[2])
//X(DOAX[2])
//X(DOA[3])
//X(DOAX[3])
//X(DOA[4])
//X(DOAX[4])
//X(DOA[5])
//X(DOAX[5])
//X(DOA[6])
//X(DOAX[6])
//X(DOA[7])
//X(DOAX[7])
//X(DOA[8])
//X(DOAX[8])
//X(DOA[9])
//X(DOAX[9])
//X(DOA[10])
//X(DOAX[10])
//X(DOA[11])
//X(DOAX[11])
//X(DOA[12])
//X(DOAX[12])
//X(DOA[13])
//X(DOAX[13])
//X(DOA[14])
//X(DOAX[14])
//X(DOA[15])
//X(DOAX[15])
//X(DOA[16])
//X(DOAX[16])
//X(DOA[17])
//X(DOAX[17])
//X(DOA[18])
//X(DOAX[18])
//X(DOA[19])
//X(DOAX[19])
//X(DOA[20])
//X(DOAX[20])
//X(DOA[21])
//X(DOAX[21])
//X(DOA[22])
//X(DOAX[22])
//X(DOA[23])
//X(DOAX[23])
//X(DOA[24])
//X(DOAX[24])
//X(DOA[25])
//X(DOAX[25])
//X(DOA[26])
//X(DOAX[26])
//X(DOA[27])
//X(DOAX[27])
//X(DOA[28])
//X(DOAX[28])
//X(DOA[29])
//X(DOAX[29])
//X(DOA[30])
//X(DOAX[30])
//X(DOA[31])
//X(DOAX[31])
//X(DOA[32])
//X(DOAX[32])
//X(DOA[33])
//X(DOAX[33])
//X(DOA[34])
//X(DOAX[34])
//X(DOA[35])
//X(DOAX[35])
//X(DOA[36])
//X(DOAX[36])
//X(DOA[37])
//X(DOAX[37])
//X(DOA[38])
//X(DOAX[38])
//X(DOA[39])
//X(DOAX[39])
//X(CLOCKA[1])
//X(CLOCKA[2])
//X(CLOCKA[3])
//X(CLOCKA[4])
//X(DOB[0])
//X(DOBX[0])
//X(DOB[1])
//X(DOBX[1])
//X(DOB[2])
//X(DOBX[2])
//X(DOB[3])
//X(DOBX[3])
//X(DOB[4])
//X(DOBX[4])
//X(DOB[5])
//X(DOBX[5])
//X(DOB[6])
//X(DOBX[6])
//X(DOB[7])
//X(DOBX[7])
//X(DOB[8])
//X(DOBX[8])
//X(DOB[9])
//X(DOBX[9])
//X(DOB[10])
//X(DOBX[10])
//X(DOB[11])
//X(DOBX[11])
//X(DOB[12])
//X(DOBX[12])
//X(DOB[13])
//X(DOBX[13])
//X(DOB[14])
//X(DOBX[14])
//X(DOB[15])
//X(DOBX[15])
//X(DOB[16])
//X(DOBX[16])
//X(DOB[17])
//X(DOBX[17])
//X(DOB[18])
//X(DOBX[18])
//X(DOB[19])
//X(DOBX[19])
//X(DOB[20])
//X(DOBX[20])
//X(DOB[21])
//X(DOBX[21])
//X(DOB[22])
//X(DOBX[22])
//X(DOB[23])
//X(DOBX[23])
//X(DOB[24])
//X(DOBX[24])
//X(DOB[25])
//X(DOBX[25])
//X(DOB[26])
//X(DOBX[26])
//X(DOB[27])
//X(DOBX[27])
//X(DOB[28])
//X(DOBX[28])
//X(DOB[29])
//X(DOBX[29])
//X(DOB[30])
//X(DOBX[30])
//X(DOB[31])
//X(DOBX[31])
//X(DOB[32])
//X(DOBX[32])
//X(DOB[33])
//X(DOBX[33])
//X(DOB[34])
//X(DOBX[34])
//X(DOB[35])
//X(DOBX[35])
//X(DOB[36])
//X(DOBX[36])
//X(DOB[37])
//X(DOBX[37])
//X(DOB[38])
//X(DOBX[38])
//X(DOB[39])
//X(DOBX[39])
//X(CLOCKB[1])
//X(CLOCKB[2])
//X(CLOCKB[3])
//X(CLOCKB[4])
//X(ECC1B_ERRA[0])
//X(ECC1B_ERRA[1])
//X(ECC1B_ERRA[2])
//X(ECC1B_ERRA[3])
//X(ECC1B_ERRB[0])
//X(ECC1B_ERRB[1])
//X(ECC1B_ERRB[2])
//X(ECC1B_ERRB[3])
//X(ECC2B_ERRA[0])
//X(ECC2B_ERRA[1])
//X(ECC2B_ERRA[2])
//X(ECC2B_ERRA[3])
//X(ECC2B_ERRB[0])
//X(ECC2B_ERRB[1])
//X(ECC2B_ERRB[2])
//X(ECC2B_ERRB[3])
//X(F_FULL[0])
//X(F_FULL[1])
//X(F_EMPTY[0])
//X(F_EMPTY[1])
//X(F_AL_FULL[0])
//X(F_AL_FULL[1])
//X(F_AL_EMPTY[0])
//X(F_AL_EMPTY[1])
//X(FWR_ERR[0])
//X(FWR_ERR[1])
//X(FRD_ERR[0])
//X(FRD_ERR[1])
//X(FWR_ADDR[0])
//X(FWR_ADDRX[0])
//X(FWR_ADDR[1])
//X(FWR_ADDRX[1])
//X(FWR_ADDR[2])
//X(FWR_ADDRX[2])
//X(FWR_ADDR[3])
//X(FWR_ADDRX[3])
//X(FWR_ADDR[4])
//X(FWR_ADDRX[4])
//X(FWR_ADDR[5])
//X(FWR_ADDRX[5])
//X(FWR_ADDR[6])
//X(FWR_ADDRX[6])
//X(FWR_ADDR[7])
//X(FWR_ADDRX[7])
//X(FWR_ADDR[8])
//X(FWR_ADDRX[8])
//X(FWR_ADDR[9])
//X(FWR_ADDRX[9])
//X(FWR_ADDR[10])
//X(FWR_ADDRX[10])
//X(FWR_ADDR[11])
//X(FWR_ADDRX[11])
//X(FWR_ADDR[12])
//X(FWR_ADDRX[12])
//X(FWR_ADDR[13])
//X(FWR_ADDRX[13])
//X(FWR_ADDR[14])
//X(FWR_ADDRX[14])
//X(FWR_ADDR[15])
//X(FWR_ADDRX[15])
//X(FRD_ADDR[0])
//X(FRD_ADDRX[0])
//X(FRD_ADDR[1])
//X(FRD_ADDRX[1])
//X(FRD_ADDR[2])
//X(FRD_ADDRX[2])
//X(FRD_ADDR[3])
//X(FRD_ADDRX[3])
//X(FRD_ADDR[4])
//X(FRD_ADDRX[4])
//X(FRD_ADDR[5])
//X(FRD_ADDRX[5])
//X(FRD_ADDR[6])
//X(FRD_ADDRX[6])
//X(FRD_ADDR[7])
//X(FRD_ADDRX[7])
//X(FRD_ADDR[8])
//X(FRD_ADDRX[8])
//X(FRD_ADDR[9])
//X(FRD_ADDRX[9])
//X(FRD_ADDR[10])
//X(FRD_ADDRX[10])
//X(FRD_ADDR[11])
//X(FRD_ADDRX[11])
//X(FRD_ADDR[12])
//X(FRD_ADDRX[12])
//X(FRD_ADDR[13])
//X(FRD_ADDRX[13])
//X(FRD_ADDR[14])
//X(FRD_ADDRX[14])
//X(FRD_ADDR[15])
//X(FRD_ADDRX[15])
gatemate: Multi die support and primitives model improvement (#1501) * SER_CLK support * Update constids * wip * CLK_FEEDBACK * Handle SER_CLK and SER_CLK_N * clangformat * Cleanup * Use _ as separator for PLL CFGs * Remove unused clocking cells * Do not use same name for IO models * Fix IDDR merge * Cleanup * Properly handle user global signals * Move signal inversion in bitstream creation * Start adding multi die support * Display die location for pins used * Do not use constant s as locations * Cleanup SB_DRIVE handling * Use DDR locations from chip database * Place only in prefered die for now * Set D2D * Fixed typos
2025-06-18 08:32:57 +02:00
//X(CLOCK1)
//X(CLOCK2)
//X(CLOCK3)
//X(CLOCK4)
Gatemate FPGA initial support (#1473) * Initial code for GateMate * Initial work on forming bitstream * Add CCF parsing * Use CCF to set IO location * Propagate errors * Restructure code * Add support for reading from config * Start adding infrastructure for reading bitstream * Fix script * GPIO initial work * Add IN1->RAM_O2 propagation * Fixed typo * Cleanup * More parameter checks * Add LVDS support * Cleanup * Keep just used connections for now * Naive lut tree CPE pack * Naive pack CC_DFF * pack DFF fixes * Handle MUX flags * Fix DFF pack * Prevent pass trough issues * Cleanup * Use device wrapper class * Update due to API changes * Use pin connection aliases * Start work on BUFG support * Fix CC_L2T5 pack * Add CPE input inverters * Constrain routes to have correct inversion state * Add clock inversion pip * Added MX2 and MX4 support * Fix script * BUFG support * debug print if route found with wrong polarity * Some CC_DFF improvements * Create reproducible chip database * Simplify inversion of special signals * Few more DFF features * Add forgotten virtual port renames * Handle muxes with constant inputs * Allow inversion for muxes * cleanup * DFF input can be constant * init DFF only when needed * cleanup * Add basic PLL support * Add some timings * Add USR_RSTN support * Display few more primitives * Use pass trough signals to validate architecture data * Use extra tile information from chip database * Updates needed for a build system changes * Implement SB_DRIVE support * Properly named configuration bits * autogenerated constids.inc * small fix * Initial code for CPE halfs * Some cleanup * make sure FFs are compatible * reverted due to db change * Merge DFF where applicable * memory allocation issue * fix * better MX2 * ram_i handling * Cleanup MX4 * Support latches * compare L_D flag as well * Move virtual pips * Naive addf pack * carry chains grouping * Keep chip database reproducible * split addf vectors * Block CPEs when GPIO is used * Prepare placement code * RAM_I/RAM_O rewrite * fix ram_i/o index * Display RAM and add new primitives * PLL wip code * CC_PLL_ADV packing * PLL handling cleanup * Add PLL comments * Keep only high fan-out BUFG * Add skeleton for tests * Utilize move_ram_o * GPIO wip * GPIO wip * PLL fixes * cleanup * FF_OBF support * Handle FF_IBF * Make SLEW FAST if not defined as in latest p_r * Make sure FF_OBF only driving GPIO * Moved pll calc into separate file * IDDR handling and started ODDR * Route DDR input for CC_ODDR * Notify error in case ODDR or IDDR are used but not with I/O pin * cleanup for CC_USR_RSTN * Extract proper RAM location for bitstream * Code cleanup * Allow auto place of pads * Use clock source flag * Configure GPIO clock signals * Handle conflicting clk * Use BUGF in proper order * Connected CLK, works without but good for debugging * CC_CFG_CTRL placement * Group RAM data 40 bytes per row * Write BRAM content * RAM wip * Use relative constraints from chipdb * fix broken build * Memory wip * Handle custom clock for memories * Support FIFO * optimize move_ram_io * Fix SR signal handling acorrding to findings * set placer beta * Pre place what we can * Revert "debug print if route found with wrong polarity" This reverts commit cf9ded2f183db0f4e85da454e5d9f2a4da3f5cfe. * Revert "Constrain routes to have correct inversion state" This reverts commit 795c284d4856ff17e37d64f013775e86f1bed803. * Remove virtual pips * Implement post processing inversion * ADDF add ability to route additional CO * Merge two ADDFs in one CPE * Added TODO * clangformat * Cleanup * Add serdes handling in config file * Cleanup * Cleanup * Cleanup * Fix in PLL handling * Fixed ADDF edge case * No need for this * Fix latch * Sanity checks * Support CC_BRAM_20K merge * Start creating testing environment * LVDS fixes * Add connection helper * Cleanup * Fix tabs * Formatting fix * Remove optimization tests for now * remove read_bitstream * removed .c_str() * Removed config parsing * using snake_case * Use bool_or_default where applicable * refactored bitstream write code * Add allow-unconstrained option * Update DFF related messages * Add clock constraint propagation --------- Co-authored-by: Lofty <dan.ravensloft@gmail.com>
2025-04-22 16:41:01 +02:00
gatemate: Enable placing RAM halfs (#1544) * gatemate: Split BRAMs into halfs * Cleanups * move code arround * optmize remapping halfs * Name RAM cells * fix cluster setting for cascade mode * attach ECC pins * rewire global clocks * bump chip database version * Fix KEEPER setting * Fix conflict check * cleanup
2025-09-02 08:03:22 +02:00
// hardware primitive RAM_HALF_U
X(RAM_HALF_U)
// RAM_HALF_U pins
//X(CLKA[0])
//X(ENA[0])
//X(GLWEA[0])
//X(CLKB[0])
//X(ENB[0])
//X(GLWEB[0])
//X(WEA[0])
//X(WEA[1])
//X(WEA[2])
//X(WEA[3])
//X(WEA[4])
//X(WEA[5])
//X(WEA[6])
//X(WEA[7])
//X(WEA[8])
//X(WEA[9])
//X(WEA[10])
//X(WEA[11])
//X(WEA[12])
//X(WEA[13])
//X(WEA[14])
//X(WEA[15])
//X(WEA[16])
//X(WEA[17])
//X(WEA[18])
//X(WEA[19])
//X(WEB[0])
//X(WEB[1])
//X(WEB[2])
//X(WEB[3])
//X(WEB[4])
//X(WEB[5])
//X(WEB[6])
//X(WEB[7])
//X(WEB[8])
//X(WEB[9])
//X(WEB[10])
//X(WEB[11])
//X(WEB[12])
//X(WEB[13])
//X(WEB[14])
//X(WEB[15])
//X(WEB[16])
//X(WEB[17])
//X(WEB[18])
//X(WEB[19])
//X(ADDRA0[0])
//X(ADDRA0[1])
//X(ADDRA0[2])
//X(ADDRA0[3])
//X(ADDRA0[4])
//X(ADDRA0[5])
//X(ADDRA0[6])
//X(ADDRA0[7])
//X(ADDRA0[8])
//X(ADDRA0[9])
//X(ADDRA0[10])
//X(ADDRA0[11])
//X(ADDRA0[12])
//X(ADDRA0[13])
//X(ADDRA0[14])
//X(ADDRA0[15])
//X(ADDRB0[0])
//X(ADDRB0[1])
//X(ADDRB0[2])
//X(ADDRB0[3])
//X(ADDRB0[4])
//X(ADDRB0[5])
//X(ADDRB0[6])
//X(ADDRB0[7])
//X(ADDRB0[8])
//X(ADDRB0[9])
//X(ADDRB0[10])
//X(ADDRB0[11])
//X(ADDRB0[12])
//X(ADDRB0[13])
//X(ADDRB0[14])
//X(ADDRB0[15])
//X(DIA[0])
//X(DIA[1])
//X(DIA[2])
//X(DIA[3])
//X(DIA[4])
//X(DIA[5])
//X(DIA[6])
//X(DIA[7])
//X(DIA[8])
//X(DIA[9])
//X(DIA[10])
//X(DIA[11])
//X(DIA[12])
//X(DIA[13])
//X(DIA[14])
//X(DIA[15])
//X(DIA[16])
//X(DIA[17])
//X(DIA[18])
//X(DIA[19])
//X(DIB[0])
//X(DIB[1])
//X(DIB[2])
//X(DIB[3])
//X(DIB[4])
//X(DIB[5])
//X(DIB[6])
//X(DIB[7])
//X(DIB[8])
//X(DIB[9])
//X(DIB[10])
//X(DIB[11])
//X(DIB[12])
//X(DIB[13])
//X(DIB[14])
//X(DIB[15])
//X(DIB[16])
//X(DIB[17])
//X(DIB[18])
//X(DIB[19])
//X(DOA[0])
//X(DOA[1])
//X(DOA[2])
//X(DOA[3])
//X(DOA[4])
//X(DOA[5])
//X(DOA[6])
//X(DOA[7])
//X(DOA[8])
//X(DOA[9])
//X(DOA[10])
//X(DOA[11])
//X(DOA[12])
//X(DOA[13])
//X(DOA[14])
//X(DOA[15])
//X(DOA[16])
//X(DOA[17])
//X(DOA[18])
//X(DOA[19])
//X(DOB[0])
//X(DOB[1])
//X(DOB[2])
//X(DOB[3])
//X(DOB[4])
//X(DOB[5])
//X(DOB[6])
//X(DOB[7])
//X(DOB[8])
//X(DOB[9])
//X(DOB[10])
//X(DOB[11])
//X(DOB[12])
//X(DOB[13])
//X(DOB[14])
//X(DOB[15])
//X(DOB[16])
//X(DOB[17])
//X(DOB[18])
//X(DOB[19])
//X(ECC1B_ERRA[0])
//X(ECC1B_ERRB[0])
//X(ECC2B_ERRA[0])
//X(ECC2B_ERRB[0])
//X(CLOCK1)
//X(CLOCK2)
//X(CLOCK3)
//X(CLOCK4)
// hardware primitive RAM_HALF_L
X(RAM_HALF_L)
// RAM_HALF_L pins
//X(CLKA[0])
//X(ENA[0])
//X(GLWEA[0])
//X(CLKB[0])
//X(ENB[0])
//X(GLWEB[0])
//X(WEA[0])
//X(WEA[1])
//X(WEA[2])
//X(WEA[3])
//X(WEA[4])
//X(WEA[5])
//X(WEA[6])
//X(WEA[7])
//X(WEA[8])
//X(WEA[9])
//X(WEA[10])
//X(WEA[11])
//X(WEA[12])
//X(WEA[13])
//X(WEA[14])
//X(WEA[15])
//X(WEA[16])
//X(WEA[17])
//X(WEA[18])
//X(WEA[19])
//X(WEB[0])
//X(WEB[1])
//X(WEB[2])
//X(WEB[3])
//X(WEB[4])
//X(WEB[5])
//X(WEB[6])
//X(WEB[7])
//X(WEB[8])
//X(WEB[9])
//X(WEB[10])
//X(WEB[11])
//X(WEB[12])
//X(WEB[13])
//X(WEB[14])
//X(WEB[15])
//X(WEB[16])
//X(WEB[17])
//X(WEB[18])
//X(WEB[19])
//X(ADDRA0[0])
//X(ADDRA0[1])
//X(ADDRA0[2])
//X(ADDRA0[3])
//X(ADDRA0[4])
//X(ADDRA0[5])
//X(ADDRA0[6])
//X(ADDRA0[7])
//X(ADDRA0[8])
//X(ADDRA0[9])
//X(ADDRA0[10])
//X(ADDRA0[11])
//X(ADDRA0[12])
//X(ADDRA0[13])
//X(ADDRA0[14])
//X(ADDRA0[15])
//X(ADDRB0[0])
//X(ADDRB0[1])
//X(ADDRB0[2])
//X(ADDRB0[3])
//X(ADDRB0[4])
//X(ADDRB0[5])
//X(ADDRB0[6])
//X(ADDRB0[7])
//X(ADDRB0[8])
//X(ADDRB0[9])
//X(ADDRB0[10])
//X(ADDRB0[11])
//X(ADDRB0[12])
//X(ADDRB0[13])
//X(ADDRB0[14])
//X(ADDRB0[15])
//X(DIA[0])
//X(DIA[1])
//X(DIA[2])
//X(DIA[3])
//X(DIA[4])
//X(DIA[5])
//X(DIA[6])
//X(DIA[7])
//X(DIA[8])
//X(DIA[9])
//X(DIA[10])
//X(DIA[11])
//X(DIA[12])
//X(DIA[13])
//X(DIA[14])
//X(DIA[15])
//X(DIA[16])
//X(DIA[17])
//X(DIA[18])
//X(DIA[19])
//X(DIB[0])
//X(DIB[1])
//X(DIB[2])
//X(DIB[3])
//X(DIB[4])
//X(DIB[5])
//X(DIB[6])
//X(DIB[7])
//X(DIB[8])
//X(DIB[9])
//X(DIB[10])
//X(DIB[11])
//X(DIB[12])
//X(DIB[13])
//X(DIB[14])
//X(DIB[15])
//X(DIB[16])
//X(DIB[17])
//X(DIB[18])
//X(DIB[19])
//X(DOA[0])
//X(DOA[1])
//X(DOA[2])
//X(DOA[3])
//X(DOA[4])
//X(DOA[5])
//X(DOA[6])
//X(DOA[7])
//X(DOA[8])
//X(DOA[9])
//X(DOA[10])
//X(DOA[11])
//X(DOA[12])
//X(DOA[13])
//X(DOA[14])
//X(DOA[15])
//X(DOA[16])
//X(DOA[17])
//X(DOA[18])
//X(DOA[19])
//X(DOB[0])
//X(DOB[1])
//X(DOB[2])
//X(DOB[3])
//X(DOB[4])
//X(DOB[5])
//X(DOB[6])
//X(DOB[7])
//X(DOB[8])
//X(DOB[9])
//X(DOB[10])
//X(DOB[11])
//X(DOB[12])
//X(DOB[13])
//X(DOB[14])
//X(DOB[15])
//X(DOB[16])
//X(DOB[17])
//X(DOB[18])
//X(DOB[19])
//X(ECC1B_ERRA[0])
//X(ECC1B_ERRB[0])
//X(ECC2B_ERRA[0])
//X(ECC2B_ERRB[0])
//X(CLOCK1)
//X(CLOCK2)
//X(CLOCK3)
//X(CLOCK4)
Gatemate FPGA initial support (#1473) * Initial code for GateMate * Initial work on forming bitstream * Add CCF parsing * Use CCF to set IO location * Propagate errors * Restructure code * Add support for reading from config * Start adding infrastructure for reading bitstream * Fix script * GPIO initial work * Add IN1->RAM_O2 propagation * Fixed typo * Cleanup * More parameter checks * Add LVDS support * Cleanup * Keep just used connections for now * Naive lut tree CPE pack * Naive pack CC_DFF * pack DFF fixes * Handle MUX flags * Fix DFF pack * Prevent pass trough issues * Cleanup * Use device wrapper class * Update due to API changes * Use pin connection aliases * Start work on BUFG support * Fix CC_L2T5 pack * Add CPE input inverters * Constrain routes to have correct inversion state * Add clock inversion pip * Added MX2 and MX4 support * Fix script * BUFG support * debug print if route found with wrong polarity * Some CC_DFF improvements * Create reproducible chip database * Simplify inversion of special signals * Few more DFF features * Add forgotten virtual port renames * Handle muxes with constant inputs * Allow inversion for muxes * cleanup * DFF input can be constant * init DFF only when needed * cleanup * Add basic PLL support * Add some timings * Add USR_RSTN support * Display few more primitives * Use pass trough signals to validate architecture data * Use extra tile information from chip database * Updates needed for a build system changes * Implement SB_DRIVE support * Properly named configuration bits * autogenerated constids.inc * small fix * Initial code for CPE halfs * Some cleanup * make sure FFs are compatible * reverted due to db change * Merge DFF where applicable * memory allocation issue * fix * better MX2 * ram_i handling * Cleanup MX4 * Support latches * compare L_D flag as well * Move virtual pips * Naive addf pack * carry chains grouping * Keep chip database reproducible * split addf vectors * Block CPEs when GPIO is used * Prepare placement code * RAM_I/RAM_O rewrite * fix ram_i/o index * Display RAM and add new primitives * PLL wip code * CC_PLL_ADV packing * PLL handling cleanup * Add PLL comments * Keep only high fan-out BUFG * Add skeleton for tests * Utilize move_ram_o * GPIO wip * GPIO wip * PLL fixes * cleanup * FF_OBF support * Handle FF_IBF * Make SLEW FAST if not defined as in latest p_r * Make sure FF_OBF only driving GPIO * Moved pll calc into separate file * IDDR handling and started ODDR * Route DDR input for CC_ODDR * Notify error in case ODDR or IDDR are used but not with I/O pin * cleanup for CC_USR_RSTN * Extract proper RAM location for bitstream * Code cleanup * Allow auto place of pads * Use clock source flag * Configure GPIO clock signals * Handle conflicting clk * Use BUGF in proper order * Connected CLK, works without but good for debugging * CC_CFG_CTRL placement * Group RAM data 40 bytes per row * Write BRAM content * RAM wip * Use relative constraints from chipdb * fix broken build * Memory wip * Handle custom clock for memories * Support FIFO * optimize move_ram_io * Fix SR signal handling acorrding to findings * set placer beta * Pre place what we can * Revert "debug print if route found with wrong polarity" This reverts commit cf9ded2f183db0f4e85da454e5d9f2a4da3f5cfe. * Revert "Constrain routes to have correct inversion state" This reverts commit 795c284d4856ff17e37d64f013775e86f1bed803. * Remove virtual pips * Implement post processing inversion * ADDF add ability to route additional CO * Merge two ADDFs in one CPE * Added TODO * clangformat * Cleanup * Add serdes handling in config file * Cleanup * Cleanup * Cleanup * Fix in PLL handling * Fixed ADDF edge case * No need for this * Fix latch * Sanity checks * Support CC_BRAM_20K merge * Start creating testing environment * LVDS fixes * Add connection helper * Cleanup * Fix tabs * Formatting fix * Remove optimization tests for now * remove read_bitstream * removed .c_str() * Removed config parsing * using snake_case * Use bool_or_default where applicable * refactored bitstream write code * Add allow-unconstrained option * Update DFF related messages * Add clock constraint propagation --------- Co-authored-by: Lofty <dan.ravensloft@gmail.com>
2025-04-22 16:41:01 +02:00
// hardware primitive SERDES
X(SERDES)
// SERDES pins
//X(TX_DETECT_RX_I)
//X(PLL_RESET_I)
gatemate: Initial SERDES support (#1476) * Initial SERDES support * use static array for default values * Split pack into multiple files * Pre-place BUFG and related cells
2025-05-06 15:56:26 +02:00
//X(REGFILE_CLK_I)
//X(TX_CLK_I)
//X(RX_CLK_I)
Gatemate FPGA initial support (#1473) * Initial code for GateMate * Initial work on forming bitstream * Add CCF parsing * Use CCF to set IO location * Propagate errors * Restructure code * Add support for reading from config * Start adding infrastructure for reading bitstream * Fix script * GPIO initial work * Add IN1->RAM_O2 propagation * Fixed typo * Cleanup * More parameter checks * Add LVDS support * Cleanup * Keep just used connections for now * Naive lut tree CPE pack * Naive pack CC_DFF * pack DFF fixes * Handle MUX flags * Fix DFF pack * Prevent pass trough issues * Cleanup * Use device wrapper class * Update due to API changes * Use pin connection aliases * Start work on BUFG support * Fix CC_L2T5 pack * Add CPE input inverters * Constrain routes to have correct inversion state * Add clock inversion pip * Added MX2 and MX4 support * Fix script * BUFG support * debug print if route found with wrong polarity * Some CC_DFF improvements * Create reproducible chip database * Simplify inversion of special signals * Few more DFF features * Add forgotten virtual port renames * Handle muxes with constant inputs * Allow inversion for muxes * cleanup * DFF input can be constant * init DFF only when needed * cleanup * Add basic PLL support * Add some timings * Add USR_RSTN support * Display few more primitives * Use pass trough signals to validate architecture data * Use extra tile information from chip database * Updates needed for a build system changes * Implement SB_DRIVE support * Properly named configuration bits * autogenerated constids.inc * small fix * Initial code for CPE halfs * Some cleanup * make sure FFs are compatible * reverted due to db change * Merge DFF where applicable * memory allocation issue * fix * better MX2 * ram_i handling * Cleanup MX4 * Support latches * compare L_D flag as well * Move virtual pips * Naive addf pack * carry chains grouping * Keep chip database reproducible * split addf vectors * Block CPEs when GPIO is used * Prepare placement code * RAM_I/RAM_O rewrite * fix ram_i/o index * Display RAM and add new primitives * PLL wip code * CC_PLL_ADV packing * PLL handling cleanup * Add PLL comments * Keep only high fan-out BUFG * Add skeleton for tests * Utilize move_ram_o * GPIO wip * GPIO wip * PLL fixes * cleanup * FF_OBF support * Handle FF_IBF * Make SLEW FAST if not defined as in latest p_r * Make sure FF_OBF only driving GPIO * Moved pll calc into separate file * IDDR handling and started ODDR * Route DDR input for CC_ODDR * Notify error in case ODDR or IDDR are used but not with I/O pin * cleanup for CC_USR_RSTN * Extract proper RAM location for bitstream * Code cleanup * Allow auto place of pads * Use clock source flag * Configure GPIO clock signals * Handle conflicting clk * Use BUGF in proper order * Connected CLK, works without but good for debugging * CC_CFG_CTRL placement * Group RAM data 40 bytes per row * Write BRAM content * RAM wip * Use relative constraints from chipdb * fix broken build * Memory wip * Handle custom clock for memories * Support FIFO * optimize move_ram_io * Fix SR signal handling acorrding to findings * set placer beta * Pre place what we can * Revert "debug print if route found with wrong polarity" This reverts commit cf9ded2f183db0f4e85da454e5d9f2a4da3f5cfe. * Revert "Constrain routes to have correct inversion state" This reverts commit 795c284d4856ff17e37d64f013775e86f1bed803. * Remove virtual pips * Implement post processing inversion * ADDF add ability to route additional CO * Merge two ADDFs in one CPE * Added TODO * clangformat * Cleanup * Add serdes handling in config file * Cleanup * Cleanup * Cleanup * Fix in PLL handling * Fixed ADDF edge case * No need for this * Fix latch * Sanity checks * Support CC_BRAM_20K merge * Start creating testing environment * LVDS fixes * Add connection helper * Cleanup * Fix tabs * Formatting fix * Remove optimization tests for now * remove read_bitstream * removed .c_str() * Removed config parsing * using snake_case * Use bool_or_default where applicable * refactored bitstream write code * Add allow-unconstrained option * Update DFF related messages * Add clock constraint propagation --------- Co-authored-by: Lofty <dan.ravensloft@gmail.com>
2025-04-22 16:41:01 +02:00
//X(REGFILE_WE_I)
//X(REGFILE_EN_I)
//X(TX_RESET_I)
//X(TX_PCS_RESET_I)
//X(TX_PMA_RESET_I)
//X(TX_PRBS_FORCE_ERR_I)
//X(TX_POLARITY_I)
//X(TX_8B10B_EN_I)
//X(RX_RESET_I)
//X(RX_PMA_RESET_I)
//X(RX_EQA_RESET_I)
//X(RX_CDR_RESET_I)
//X(RX_PCS_RESET_I)
//X(RX_BUF_RESET_I)
//X(RX_PRBS_CNT_RESET_I)
//X(RX_EN_EI_DETECTOR_I)
//X(RX_COMMA_DETECT_EN_I)
//X(RX_SLIDE_I)
//X(RX_POLARITY_I)
//X(RX_8B10B_EN_I)
//X(RX_MCOMMA_ALIGN_I)
//X(RX_PCOMMA_ALIGN_I)
//X(RX_NOT_IN_TABLE_O[7])
//X(RX_NOT_IN_TABLE_O[6])
//X(RX_NOT_IN_TABLE_O[5])
//X(RX_NOT_IN_TABLE_O[4])
//X(RX_NOT_IN_TABLE_O[3])
//X(RX_NOT_IN_TABLE_O[2])
//X(RX_NOT_IN_TABLE_O[1])
//X(RX_NOT_IN_TABLE_O[0])
//X(RX_CHAR_IS_COMMA_O[7])
//X(RX_CHAR_IS_COMMA_O[6])
//X(RX_CHAR_IS_COMMA_O[5])
//X(RX_CHAR_IS_COMMA_O[4])
//X(RX_CHAR_IS_COMMA_O[3])
//X(RX_CHAR_IS_COMMA_O[2])
//X(RX_CHAR_IS_COMMA_O[1])
//X(RX_CHAR_IS_COMMA_O[0])
//X(REGFILE_ADDR_I[7])
//X(REGFILE_ADDR_I[6])
//X(REGFILE_ADDR_I[5])
//X(REGFILE_ADDR_I[4])
//X(REGFILE_ADDR_I[3])
//X(REGFILE_ADDR_I[2])
//X(REGFILE_ADDR_I[1])
//X(REGFILE_ADDR_I[0])
//X(TX_CHAR_IS_K_I[7])
//X(TX_CHAR_IS_K_I[6])
//X(TX_CHAR_IS_K_I[5])
//X(TX_CHAR_IS_K_I[4])
//X(TX_CHAR_IS_K_I[3])
//X(TX_CHAR_IS_K_I[2])
//X(TX_CHAR_IS_K_I[1])
//X(TX_CHAR_IS_K_I[0])
//X(TX_8B10B_BYPASS_I[7])
//X(TX_8B10B_BYPASS_I[6])
//X(TX_8B10B_BYPASS_I[5])
//X(TX_8B10B_BYPASS_I[4])
//X(TX_8B10B_BYPASS_I[3])
//X(TX_8B10B_BYPASS_I[2])
//X(TX_8B10B_BYPASS_I[1])
//X(TX_8B10B_BYPASS_I[0])
//X(RX_8B10B_BYPASS_I[7])
//X(RX_8B10B_BYPASS_I[6])
//X(RX_8B10B_BYPASS_I[5])
//X(RX_8B10B_BYPASS_I[4])
//X(RX_8B10B_BYPASS_I[3])
//X(RX_8B10B_BYPASS_I[2])
//X(RX_8B10B_BYPASS_I[1])
//X(RX_8B10B_BYPASS_I[0])
//X(TX_CHAR_DISPMODE_I[7])
//X(TX_CHAR_DISPMODE_I[6])
//X(TX_CHAR_DISPMODE_I[5])
//X(TX_CHAR_DISPMODE_I[4])
//X(TX_CHAR_DISPMODE_I[3])
//X(TX_CHAR_DISPMODE_I[2])
//X(TX_CHAR_DISPMODE_I[1])
//X(TX_CHAR_DISPMODE_I[0])
//X(TX_CHAR_DISPVAL_I[7])
//X(TX_CHAR_DISPVAL_I[6])
//X(TX_CHAR_DISPVAL_I[5])
//X(TX_CHAR_DISPVAL_I[4])
//X(TX_CHAR_DISPVAL_I[3])
//X(TX_CHAR_DISPVAL_I[2])
//X(TX_CHAR_DISPVAL_I[1])
//X(TX_CHAR_DISPVAL_I[0])
//X(TX_DATA_I[63])
//X(TX_DATA_I[62])
//X(TX_DATA_I[61])
//X(TX_DATA_I[60])
//X(TX_DATA_I[59])
//X(TX_DATA_I[58])
//X(TX_DATA_I[57])
//X(TX_DATA_I[56])
//X(TX_DATA_I[55])
//X(TX_DATA_I[54])
//X(TX_DATA_I[53])
//X(TX_DATA_I[52])
//X(TX_DATA_I[51])
//X(TX_DATA_I[50])
//X(TX_DATA_I[49])
//X(TX_DATA_I[48])
//X(TX_DATA_I[47])
//X(TX_DATA_I[46])
//X(TX_DATA_I[45])
//X(TX_DATA_I[44])
//X(TX_DATA_I[43])
//X(TX_DATA_I[42])
//X(TX_DATA_I[41])
//X(TX_DATA_I[40])
//X(TX_DATA_I[39])
//X(TX_DATA_I[38])
//X(TX_DATA_I[37])
//X(TX_DATA_I[36])
//X(TX_DATA_I[35])
//X(TX_DATA_I[34])
//X(TX_DATA_I[33])
//X(TX_DATA_I[32])
//X(TX_DATA_I[31])
//X(TX_DATA_I[30])
//X(TX_DATA_I[29])
//X(TX_DATA_I[28])
//X(TX_DATA_I[27])
//X(TX_DATA_I[26])
//X(TX_DATA_I[25])
//X(TX_DATA_I[24])
//X(TX_DATA_I[23])
//X(TX_DATA_I[22])
//X(TX_DATA_I[21])
//X(TX_DATA_I[20])
//X(TX_DATA_I[19])
//X(TX_DATA_I[18])
//X(TX_DATA_I[17])
//X(TX_DATA_I[16])
//X(TX_DATA_I[15])
//X(TX_DATA_I[14])
//X(TX_DATA_I[13])
//X(TX_DATA_I[12])
//X(TX_DATA_I[11])
//X(TX_DATA_I[10])
//X(TX_DATA_I[9])
//X(TX_DATA_I[8])
//X(TX_DATA_I[7])
//X(TX_DATA_I[6])
//X(TX_DATA_I[5])
//X(TX_DATA_I[4])
//X(TX_DATA_I[3])
//X(TX_DATA_I[2])
//X(TX_DATA_I[1])
//X(TX_DATA_I[0])
//X(REGFILE_DO_O[15])
//X(REGFILE_DO_O[14])
//X(REGFILE_DO_O[13])
//X(REGFILE_DO_O[12])
//X(REGFILE_DO_O[11])
//X(REGFILE_DO_O[10])
//X(REGFILE_DO_O[9])
//X(REGFILE_DO_O[8])
//X(REGFILE_DO_O[7])
//X(REGFILE_DO_O[6])
//X(REGFILE_DO_O[5])
//X(REGFILE_DO_O[4])
//X(REGFILE_DO_O[3])
//X(REGFILE_DO_O[2])
//X(REGFILE_DO_O[1])
//X(REGFILE_DO_O[0])
//X(REGFILE_DI_I[15])
//X(REGFILE_DI_I[14])
//X(REGFILE_DI_I[13])
//X(REGFILE_DI_I[12])
//X(REGFILE_DI_I[11])
//X(REGFILE_DI_I[10])
//X(REGFILE_DI_I[9])
//X(REGFILE_DI_I[8])
//X(REGFILE_DI_I[7])
//X(REGFILE_DI_I[6])
//X(REGFILE_DI_I[5])
//X(REGFILE_DI_I[4])
//X(REGFILE_DI_I[3])
//X(REGFILE_DI_I[2])
//X(REGFILE_DI_I[1])
//X(REGFILE_DI_I[0])
//X(REGFILE_MASK_I[15])
//X(REGFILE_MASK_I[14])
//X(REGFILE_MASK_I[13])
//X(REGFILE_MASK_I[12])
//X(REGFILE_MASK_I[11])
//X(REGFILE_MASK_I[10])
//X(REGFILE_MASK_I[9])
//X(REGFILE_MASK_I[8])
//X(REGFILE_MASK_I[7])
//X(REGFILE_MASK_I[6])
//X(REGFILE_MASK_I[5])
//X(REGFILE_MASK_I[4])
//X(REGFILE_MASK_I[3])
//X(REGFILE_MASK_I[2])
//X(REGFILE_MASK_I[1])
//X(REGFILE_MASK_I[0])
//X(RX_CHAR_IS_K_O[7])
//X(RX_CHAR_IS_K_O[6])
//X(RX_CHAR_IS_K_O[5])
//X(RX_CHAR_IS_K_O[4])
//X(RX_CHAR_IS_K_O[3])
//X(RX_CHAR_IS_K_O[2])
//X(RX_CHAR_IS_K_O[1])
//X(RX_CHAR_IS_K_O[0])
//X(RX_DISP_ERR_O[7])
//X(RX_DISP_ERR_O[6])
//X(RX_DISP_ERR_O[5])
//X(RX_DISP_ERR_O[4])
//X(RX_DISP_ERR_O[3])
//X(RX_DISP_ERR_O[2])
//X(RX_DISP_ERR_O[1])
//X(RX_DISP_ERR_O[0])
//X(RX_DATA_O[63])
//X(RX_DATA_O[62])
//X(RX_DATA_O[61])
//X(RX_DATA_O[60])
//X(RX_DATA_O[59])
//X(RX_DATA_O[58])
//X(RX_DATA_O[57])
//X(RX_DATA_O[56])
//X(RX_DATA_O[55])
//X(RX_DATA_O[54])
//X(RX_DATA_O[53])
//X(RX_DATA_O[52])
//X(RX_DATA_O[51])
//X(RX_DATA_O[50])
//X(RX_DATA_O[49])
//X(RX_DATA_O[48])
//X(RX_DATA_O[47])
//X(RX_DATA_O[46])
//X(RX_DATA_O[45])
//X(RX_DATA_O[44])
//X(RX_DATA_O[43])
//X(RX_DATA_O[42])
//X(RX_DATA_O[41])
//X(RX_DATA_O[40])
//X(RX_DATA_O[39])
//X(RX_DATA_O[38])
//X(RX_DATA_O[37])
//X(RX_DATA_O[36])
//X(RX_DATA_O[35])
//X(RX_DATA_O[34])
//X(RX_DATA_O[33])
//X(RX_DATA_O[32])
//X(RX_DATA_O[31])
//X(RX_DATA_O[30])
//X(RX_DATA_O[29])
//X(RX_DATA_O[28])
//X(RX_DATA_O[27])
//X(RX_DATA_O[26])
//X(RX_DATA_O[25])
//X(RX_DATA_O[24])
//X(RX_DATA_O[23])
//X(RX_DATA_O[22])
//X(RX_DATA_O[21])
//X(RX_DATA_O[20])
//X(RX_DATA_O[19])
//X(RX_DATA_O[18])
//X(RX_DATA_O[17])
//X(RX_DATA_O[16])
//X(RX_DATA_O[15])
//X(RX_DATA_O[14])
//X(RX_DATA_O[13])
//X(RX_DATA_O[12])
//X(RX_DATA_O[11])
//X(RX_DATA_O[10])
//X(RX_DATA_O[9])
//X(RX_DATA_O[8])
//X(RX_DATA_O[7])
//X(RX_DATA_O[6])
//X(RX_DATA_O[5])
//X(RX_DATA_O[4])
//X(RX_DATA_O[3])
//X(RX_DATA_O[2])
//X(RX_DATA_O[1])
//X(RX_DATA_O[0])
gatemate: Initial SERDES support (#1476) * Initial SERDES support * use static array for default values * Split pack into multiple files * Pre-place BUFG and related cells
2025-05-06 15:56:26 +02:00
//X(TX_DETECT_RX_DONE_O)
//X(TX_DETECT_RX_PRESENT_O)
//X(RX_CLK_O)
//X(PLL_CLK_O)
Gatemate FPGA initial support (#1473) * Initial code for GateMate * Initial work on forming bitstream * Add CCF parsing * Use CCF to set IO location * Propagate errors * Restructure code * Add support for reading from config * Start adding infrastructure for reading bitstream * Fix script * GPIO initial work * Add IN1->RAM_O2 propagation * Fixed typo * Cleanup * More parameter checks * Add LVDS support * Cleanup * Keep just used connections for now * Naive lut tree CPE pack * Naive pack CC_DFF * pack DFF fixes * Handle MUX flags * Fix DFF pack * Prevent pass trough issues * Cleanup * Use device wrapper class * Update due to API changes * Use pin connection aliases * Start work on BUFG support * Fix CC_L2T5 pack * Add CPE input inverters * Constrain routes to have correct inversion state * Add clock inversion pip * Added MX2 and MX4 support * Fix script * BUFG support * debug print if route found with wrong polarity * Some CC_DFF improvements * Create reproducible chip database * Simplify inversion of special signals * Few more DFF features * Add forgotten virtual port renames * Handle muxes with constant inputs * Allow inversion for muxes * cleanup * DFF input can be constant * init DFF only when needed * cleanup * Add basic PLL support * Add some timings * Add USR_RSTN support * Display few more primitives * Use pass trough signals to validate architecture data * Use extra tile information from chip database * Updates needed for a build system changes * Implement SB_DRIVE support * Properly named configuration bits * autogenerated constids.inc * small fix * Initial code for CPE halfs * Some cleanup * make sure FFs are compatible * reverted due to db change * Merge DFF where applicable * memory allocation issue * fix * better MX2 * ram_i handling * Cleanup MX4 * Support latches * compare L_D flag as well * Move virtual pips * Naive addf pack * carry chains grouping * Keep chip database reproducible * split addf vectors * Block CPEs when GPIO is used * Prepare placement code * RAM_I/RAM_O rewrite * fix ram_i/o index * Display RAM and add new primitives * PLL wip code * CC_PLL_ADV packing * PLL handling cleanup * Add PLL comments * Keep only high fan-out BUFG * Add skeleton for tests * Utilize move_ram_o * GPIO wip * GPIO wip * PLL fixes * cleanup * FF_OBF support * Handle FF_IBF * Make SLEW FAST if not defined as in latest p_r * Make sure FF_OBF only driving GPIO * Moved pll calc into separate file * IDDR handling and started ODDR * Route DDR input for CC_ODDR * Notify error in case ODDR or IDDR are used but not with I/O pin * cleanup for CC_USR_RSTN * Extract proper RAM location for bitstream * Code cleanup * Allow auto place of pads * Use clock source flag * Configure GPIO clock signals * Handle conflicting clk * Use BUGF in proper order * Connected CLK, works without but good for debugging * CC_CFG_CTRL placement * Group RAM data 40 bytes per row * Write BRAM content * RAM wip * Use relative constraints from chipdb * fix broken build * Memory wip * Handle custom clock for memories * Support FIFO * optimize move_ram_io * Fix SR signal handling acorrding to findings * set placer beta * Pre place what we can * Revert "debug print if route found with wrong polarity" This reverts commit cf9ded2f183db0f4e85da454e5d9f2a4da3f5cfe. * Revert "Constrain routes to have correct inversion state" This reverts commit 795c284d4856ff17e37d64f013775e86f1bed803. * Remove virtual pips * Implement post processing inversion * ADDF add ability to route additional CO * Merge two ADDFs in one CPE * Added TODO * clangformat * Cleanup * Add serdes handling in config file * Cleanup * Cleanup * Cleanup * Fix in PLL handling * Fixed ADDF edge case * No need for this * Fix latch * Sanity checks * Support CC_BRAM_20K merge * Start creating testing environment * LVDS fixes * Add connection helper * Cleanup * Fix tabs * Formatting fix * Remove optimization tests for now * remove read_bitstream * removed .c_str() * Removed config parsing * using snake_case * Use bool_or_default where applicable * refactored bitstream write code * Add allow-unconstrained option * Update DFF related messages * Add clock constraint propagation --------- Co-authored-by: Lofty <dan.ravensloft@gmail.com>
2025-04-22 16:41:01 +02:00
//X(TX_BUF_ERR_O)
gatemate: Initial SERDES support (#1476) * Initial SERDES support * use static array for default values * Split pack into multiple files * Pre-place BUFG and related cells
2025-05-06 15:56:26 +02:00
//X(TX_RESET_DONE_O)
Gatemate FPGA initial support (#1473) * Initial code for GateMate * Initial work on forming bitstream * Add CCF parsing * Use CCF to set IO location * Propagate errors * Restructure code * Add support for reading from config * Start adding infrastructure for reading bitstream * Fix script * GPIO initial work * Add IN1->RAM_O2 propagation * Fixed typo * Cleanup * More parameter checks * Add LVDS support * Cleanup * Keep just used connections for now * Naive lut tree CPE pack * Naive pack CC_DFF * pack DFF fixes * Handle MUX flags * Fix DFF pack * Prevent pass trough issues * Cleanup * Use device wrapper class * Update due to API changes * Use pin connection aliases * Start work on BUFG support * Fix CC_L2T5 pack * Add CPE input inverters * Constrain routes to have correct inversion state * Add clock inversion pip * Added MX2 and MX4 support * Fix script * BUFG support * debug print if route found with wrong polarity * Some CC_DFF improvements * Create reproducible chip database * Simplify inversion of special signals * Few more DFF features * Add forgotten virtual port renames * Handle muxes with constant inputs * Allow inversion for muxes * cleanup * DFF input can be constant * init DFF only when needed * cleanup * Add basic PLL support * Add some timings * Add USR_RSTN support * Display few more primitives * Use pass trough signals to validate architecture data * Use extra tile information from chip database * Updates needed for a build system changes * Implement SB_DRIVE support * Properly named configuration bits * autogenerated constids.inc * small fix * Initial code for CPE halfs * Some cleanup * make sure FFs are compatible * reverted due to db change * Merge DFF where applicable * memory allocation issue * fix * better MX2 * ram_i handling * Cleanup MX4 * Support latches * compare L_D flag as well * Move virtual pips * Naive addf pack * carry chains grouping * Keep chip database reproducible * split addf vectors * Block CPEs when GPIO is used * Prepare placement code * RAM_I/RAM_O rewrite * fix ram_i/o index * Display RAM and add new primitives * PLL wip code * CC_PLL_ADV packing * PLL handling cleanup * Add PLL comments * Keep only high fan-out BUFG * Add skeleton for tests * Utilize move_ram_o * GPIO wip * GPIO wip * PLL fixes * cleanup * FF_OBF support * Handle FF_IBF * Make SLEW FAST if not defined as in latest p_r * Make sure FF_OBF only driving GPIO * Moved pll calc into separate file * IDDR handling and started ODDR * Route DDR input for CC_ODDR * Notify error in case ODDR or IDDR are used but not with I/O pin * cleanup for CC_USR_RSTN * Extract proper RAM location for bitstream * Code cleanup * Allow auto place of pads * Use clock source flag * Configure GPIO clock signals * Handle conflicting clk * Use BUGF in proper order * Connected CLK, works without but good for debugging * CC_CFG_CTRL placement * Group RAM data 40 bytes per row * Write BRAM content * RAM wip * Use relative constraints from chipdb * fix broken build * Memory wip * Handle custom clock for memories * Support FIFO * optimize move_ram_io * Fix SR signal handling acorrding to findings * set placer beta * Pre place what we can * Revert "debug print if route found with wrong polarity" This reverts commit cf9ded2f183db0f4e85da454e5d9f2a4da3f5cfe. * Revert "Constrain routes to have correct inversion state" This reverts commit 795c284d4856ff17e37d64f013775e86f1bed803. * Remove virtual pips * Implement post processing inversion * ADDF add ability to route additional CO * Merge two ADDFs in one CPE * Added TODO * clangformat * Cleanup * Add serdes handling in config file * Cleanup * Cleanup * Cleanup * Fix in PLL handling * Fixed ADDF edge case * No need for this * Fix latch * Sanity checks * Support CC_BRAM_20K merge * Start creating testing environment * LVDS fixes * Add connection helper * Cleanup * Fix tabs * Formatting fix * Remove optimization tests for now * remove read_bitstream * removed .c_str() * Removed config parsing * using snake_case * Use bool_or_default where applicable * refactored bitstream write code * Add allow-unconstrained option * Update DFF related messages * Add clock constraint propagation --------- Co-authored-by: Lofty <dan.ravensloft@gmail.com>
2025-04-22 16:41:01 +02:00
//X(REGFILE_RDY_O)
//X(RX_PRBS_ERR_O)
//X(RX_BUF_ERR_O)
//X(RX_BYTE_IS_ALIGNED_O)
//X(RX_BYTE_REALIGN_O)
gatemate: Initial SERDES support (#1476) * Initial SERDES support * use static array for default values * Split pack into multiple files * Pre-place BUFG and related cells
2025-05-06 15:56:26 +02:00
//X(RX_RESET_DONE_O)
Gatemate FPGA initial support (#1473) * Initial code for GateMate * Initial work on forming bitstream * Add CCF parsing * Use CCF to set IO location * Propagate errors * Restructure code * Add support for reading from config * Start adding infrastructure for reading bitstream * Fix script * GPIO initial work * Add IN1->RAM_O2 propagation * Fixed typo * Cleanup * More parameter checks * Add LVDS support * Cleanup * Keep just used connections for now * Naive lut tree CPE pack * Naive pack CC_DFF * pack DFF fixes * Handle MUX flags * Fix DFF pack * Prevent pass trough issues * Cleanup * Use device wrapper class * Update due to API changes * Use pin connection aliases * Start work on BUFG support * Fix CC_L2T5 pack * Add CPE input inverters * Constrain routes to have correct inversion state * Add clock inversion pip * Added MX2 and MX4 support * Fix script * BUFG support * debug print if route found with wrong polarity * Some CC_DFF improvements * Create reproducible chip database * Simplify inversion of special signals * Few more DFF features * Add forgotten virtual port renames * Handle muxes with constant inputs * Allow inversion for muxes * cleanup * DFF input can be constant * init DFF only when needed * cleanup * Add basic PLL support * Add some timings * Add USR_RSTN support * Display few more primitives * Use pass trough signals to validate architecture data * Use extra tile information from chip database * Updates needed for a build system changes * Implement SB_DRIVE support * Properly named configuration bits * autogenerated constids.inc * small fix * Initial code for CPE halfs * Some cleanup * make sure FFs are compatible * reverted due to db change * Merge DFF where applicable * memory allocation issue * fix * better MX2 * ram_i handling * Cleanup MX4 * Support latches * compare L_D flag as well * Move virtual pips * Naive addf pack * carry chains grouping * Keep chip database reproducible * split addf vectors * Block CPEs when GPIO is used * Prepare placement code * RAM_I/RAM_O rewrite * fix ram_i/o index * Display RAM and add new primitives * PLL wip code * CC_PLL_ADV packing * PLL handling cleanup * Add PLL comments * Keep only high fan-out BUFG * Add skeleton for tests * Utilize move_ram_o * GPIO wip * GPIO wip * PLL fixes * cleanup * FF_OBF support * Handle FF_IBF * Make SLEW FAST if not defined as in latest p_r * Make sure FF_OBF only driving GPIO * Moved pll calc into separate file * IDDR handling and started ODDR * Route DDR input for CC_ODDR * Notify error in case ODDR or IDDR are used but not with I/O pin * cleanup for CC_USR_RSTN * Extract proper RAM location for bitstream * Code cleanup * Allow auto place of pads * Use clock source flag * Configure GPIO clock signals * Handle conflicting clk * Use BUGF in proper order * Connected CLK, works without but good for debugging * CC_CFG_CTRL placement * Group RAM data 40 bytes per row * Write BRAM content * RAM wip * Use relative constraints from chipdb * fix broken build * Memory wip * Handle custom clock for memories * Support FIFO * optimize move_ram_io * Fix SR signal handling acorrding to findings * set placer beta * Pre place what we can * Revert "debug print if route found with wrong polarity" This reverts commit cf9ded2f183db0f4e85da454e5d9f2a4da3f5cfe. * Revert "Constrain routes to have correct inversion state" This reverts commit 795c284d4856ff17e37d64f013775e86f1bed803. * Remove virtual pips * Implement post processing inversion * ADDF add ability to route additional CO * Merge two ADDFs in one CPE * Added TODO * clangformat * Cleanup * Add serdes handling in config file * Cleanup * Cleanup * Cleanup * Fix in PLL handling * Fixed ADDF edge case * No need for this * Fix latch * Sanity checks * Support CC_BRAM_20K merge * Start creating testing environment * LVDS fixes * Add connection helper * Cleanup * Fix tabs * Formatting fix * Remove optimization tests for now * remove read_bitstream * removed .c_str() * Removed config parsing * using snake_case * Use bool_or_default where applicable * refactored bitstream write code * Add allow-unconstrained option * Update DFF related messages * Add clock constraint propagation --------- Co-authored-by: Lofty <dan.ravensloft@gmail.com>
2025-04-22 16:41:01 +02:00
//X(RX_EI_EN_O)
//X(LOOPBACK_I[2])
//X(LOOPBACK_I[1])
//X(LOOPBACK_I[0])
//X(TX_PRBS_SEL_I[2])
//X(TX_PRBS_SEL_I[1])
//X(TX_PRBS_SEL_I[0])
//X(RX_PRBS_SEL_I[2])
//X(RX_PRBS_SEL_I[1])
//X(RX_PRBS_SEL_I[0])
gatemate: Initial SERDES support (#1476) * Initial SERDES support * use static array for default values * Split pack into multiple files * Pre-place BUFG and related cells
2025-05-06 15:56:26 +02:00
//X(TX_POWER_DOWN_N_I)
//X(RX_POWER_DOWN_N_I)
Gatemate FPGA initial support (#1473) * Initial code for GateMate * Initial work on forming bitstream * Add CCF parsing * Use CCF to set IO location * Propagate errors * Restructure code * Add support for reading from config * Start adding infrastructure for reading bitstream * Fix script * GPIO initial work * Add IN1->RAM_O2 propagation * Fixed typo * Cleanup * More parameter checks * Add LVDS support * Cleanup * Keep just used connections for now * Naive lut tree CPE pack * Naive pack CC_DFF * pack DFF fixes * Handle MUX flags * Fix DFF pack * Prevent pass trough issues * Cleanup * Use device wrapper class * Update due to API changes * Use pin connection aliases * Start work on BUFG support * Fix CC_L2T5 pack * Add CPE input inverters * Constrain routes to have correct inversion state * Add clock inversion pip * Added MX2 and MX4 support * Fix script * BUFG support * debug print if route found with wrong polarity * Some CC_DFF improvements * Create reproducible chip database * Simplify inversion of special signals * Few more DFF features * Add forgotten virtual port renames * Handle muxes with constant inputs * Allow inversion for muxes * cleanup * DFF input can be constant * init DFF only when needed * cleanup * Add basic PLL support * Add some timings * Add USR_RSTN support * Display few more primitives * Use pass trough signals to validate architecture data * Use extra tile information from chip database * Updates needed for a build system changes * Implement SB_DRIVE support * Properly named configuration bits * autogenerated constids.inc * small fix * Initial code for CPE halfs * Some cleanup * make sure FFs are compatible * reverted due to db change * Merge DFF where applicable * memory allocation issue * fix * better MX2 * ram_i handling * Cleanup MX4 * Support latches * compare L_D flag as well * Move virtual pips * Naive addf pack * carry chains grouping * Keep chip database reproducible * split addf vectors * Block CPEs when GPIO is used * Prepare placement code * RAM_I/RAM_O rewrite * fix ram_i/o index * Display RAM and add new primitives * PLL wip code * CC_PLL_ADV packing * PLL handling cleanup * Add PLL comments * Keep only high fan-out BUFG * Add skeleton for tests * Utilize move_ram_o * GPIO wip * GPIO wip * PLL fixes * cleanup * FF_OBF support * Handle FF_IBF * Make SLEW FAST if not defined as in latest p_r * Make sure FF_OBF only driving GPIO * Moved pll calc into separate file * IDDR handling and started ODDR * Route DDR input for CC_ODDR * Notify error in case ODDR or IDDR are used but not with I/O pin * cleanup for CC_USR_RSTN * Extract proper RAM location for bitstream * Code cleanup * Allow auto place of pads * Use clock source flag * Configure GPIO clock signals * Handle conflicting clk * Use BUGF in proper order * Connected CLK, works without but good for debugging * CC_CFG_CTRL placement * Group RAM data 40 bytes per row * Write BRAM content * RAM wip * Use relative constraints from chipdb * fix broken build * Memory wip * Handle custom clock for memories * Support FIFO * optimize move_ram_io * Fix SR signal handling acorrding to findings * set placer beta * Pre place what we can * Revert "debug print if route found with wrong polarity" This reverts commit cf9ded2f183db0f4e85da454e5d9f2a4da3f5cfe. * Revert "Constrain routes to have correct inversion state" This reverts commit 795c284d4856ff17e37d64f013775e86f1bed803. * Remove virtual pips * Implement post processing inversion * ADDF add ability to route additional CO * Merge two ADDFs in one CPE * Added TODO * clangformat * Cleanup * Add serdes handling in config file * Cleanup * Cleanup * Cleanup * Fix in PLL handling * Fixed ADDF edge case * No need for this * Fix latch * Sanity checks * Support CC_BRAM_20K merge * Start creating testing environment * LVDS fixes * Add connection helper * Cleanup * Fix tabs * Formatting fix * Remove optimization tests for now * remove read_bitstream * removed .c_str() * Removed config parsing * using snake_case * Use bool_or_default where applicable * refactored bitstream write code * Add allow-unconstrained option * Update DFF related messages * Add clock constraint propagation --------- Co-authored-by: Lofty <dan.ravensloft@gmail.com>
2025-04-22 16:41:01 +02:00
//X(TX_ELEC_IDLE_I)
// end of autogenerated items
// CPE configuration parameters
//X(INIT_L00)
//X(INIT_L01)
//X(INIT_L02)
//X(INIT_L03)
//X(INIT_L10)
//X(INIT_L11)
//X(INIT_L20)
X(INIT_L30)
X(C_I1)
X(C_I2)
X(C_I3)
X(C_I4)
X(C_FUNCTION)
X(C_COMP)
X(C_COMP_I)
X(C_HORIZ)
X(C_SELX)
X(C_SELY1)
X(C_SELY2)
X(C_SEL_C)
X(C_SEL_P)
X(C_Y12)
X(C_CX_I)
X(C_CY1_I)
X(C_CY2_I)
X(C_PX_I)
X(C_PY1_I)
X(C_PY2_I)
X(C_C_P)
X(C_2D_IN)
X(C_SN)
X(C_O1)
X(C_O2)
X(C_BR)
X(C_CPE_CLK)
X(C_CPE_EN)
X(C_CPE_RES)
X(C_CPE_SET)
X(C_RAM_I1)
X(C_RAM_I2)
X(C_RAM_O1)
X(C_RAM_O2)
X(C_L_D)
X(C_EN_SR)
X(C_CLKSEL)
X(C_ENSEL)
X(FF_INIT)
// GPIO configuration parameters
X(OPEN_DRAIN)
//X(SLEW)
//X(DRIVE)
X(INPUT_ENABLE)
//X(PULLDOWN)
//X(PULLUP)
//X(SCHMITT_TRIGGER)
X(OUT_SIGNAL)
X(OUT1_4)
X(OUT2_3)
X(OUT23_14_SEL)
X(USE_CFG_BIT)
X(USE_DDR)
X(SEL_IN_CLOCK)
X(SEL_OUT_CLOCK)
X(OE_ENABLE)
X(OE_SIGNAL)
X(OUT1_FF)
X(OUT2_FF)
X(IN1_FF)
X(IN2_FF)
X(OUT_CLOCK)
X(INV_OUT1_CLOCK)
X(INV_OUT2_CLOCK)
X(IN_CLOCK)
X(INV_IN1_CLOCK)
X(INV_IN2_CLOCK)
//X(DELAY_OBF)
//X(DELAY_IBF)
X(LVDS_EN)
//X(LVDS_BOOST)
X(LVDS_IE)
//X(LVDS_RTERM)
Use improved CPE model (#1503) * CPE mapping improvements * Use CP_OUT for adders * Fixes * Small fixes * Cleanups * Cleanup * Cleanups * Fixes * Fixes * Optimize * Cleanup * clangformat * Cleanup * Cleanup * Bump required version of database * Cleanup * Resolve name conflicts * Fix signal routing * Make CPE_LATCH separate * Add more timings models, need updated values * Fixed warning * multiplier support from lofty/gatemate-mult * explicitly zero some params in B passthrough * comment the relevant CPE inputs in check_multipliers * Rename some of bels * remove _lower from name * refactor multiplier checking * Revert "remove _lower from name" This reverts commit daa1041bdf855b664c8f6462e1ed994459239b9c. * Fixe net name to be unique * Make sure we at least generate bitstream with all info * Simplify zero * Bounded cell type in gui * typo fix * Remove A passthrough inversion option * Clean up CarryGenCell config * Update a passthru to use new primitives * Cleanup for adders * Clean up MsbRoutingCell * Cleanup * Refactor A connection code * Make it more as in PR #1513 * Added cplines to bpassthru and fixed constant driver for A * Add parts * Added comp out connections * clangformat * clangformat * Clean up B passthrough connections * wire up a bunch of intermediate signals * Bit of cleanup * handing of C_EN_IN * C_EN_CIN fixes * connect f_route to its lines * fix cite for FRoutingCell * fixup, oops * connect multfab to its lines * Commented line * Connect CPOUTs * Handle C_I params * connect CINY1 for CarryGenCell * fix carry gen CINX * Update L2T4 model * Updates for ADDCIN * clangformat * fix some issues with multfab and f_route * look at C_I when doing inversion * Only set some C_I signals when used * Fix one more place * do not use cplines so we can merge in one cell * Cover cases that could be optimized out * clangformat * Cleanups * Disable multiplier usage for now --------- Co-authored-by: Lofty <dan.ravensloft@gmail.com>
2025-07-07 10:14:48 +02:00
X(CPE_LT)
X(CPE_FF)
X(CPE_RAMIO)
X(CPE_RAMI)
X(CPE_RAMO)
Gatemate FPGA initial support (#1473) * Initial code for GateMate * Initial work on forming bitstream * Add CCF parsing * Use CCF to set IO location * Propagate errors * Restructure code * Add support for reading from config * Start adding infrastructure for reading bitstream * Fix script * GPIO initial work * Add IN1->RAM_O2 propagation * Fixed typo * Cleanup * More parameter checks * Add LVDS support * Cleanup * Keep just used connections for now * Naive lut tree CPE pack * Naive pack CC_DFF * pack DFF fixes * Handle MUX flags * Fix DFF pack * Prevent pass trough issues * Cleanup * Use device wrapper class * Update due to API changes * Use pin connection aliases * Start work on BUFG support * Fix CC_L2T5 pack * Add CPE input inverters * Constrain routes to have correct inversion state * Add clock inversion pip * Added MX2 and MX4 support * Fix script * BUFG support * debug print if route found with wrong polarity * Some CC_DFF improvements * Create reproducible chip database * Simplify inversion of special signals * Few more DFF features * Add forgotten virtual port renames * Handle muxes with constant inputs * Allow inversion for muxes * cleanup * DFF input can be constant * init DFF only when needed * cleanup * Add basic PLL support * Add some timings * Add USR_RSTN support * Display few more primitives * Use pass trough signals to validate architecture data * Use extra tile information from chip database * Updates needed for a build system changes * Implement SB_DRIVE support * Properly named configuration bits * autogenerated constids.inc * small fix * Initial code for CPE halfs * Some cleanup * make sure FFs are compatible * reverted due to db change * Merge DFF where applicable * memory allocation issue * fix * better MX2 * ram_i handling * Cleanup MX4 * Support latches * compare L_D flag as well * Move virtual pips * Naive addf pack * carry chains grouping * Keep chip database reproducible * split addf vectors * Block CPEs when GPIO is used * Prepare placement code * RAM_I/RAM_O rewrite * fix ram_i/o index * Display RAM and add new primitives * PLL wip code * CC_PLL_ADV packing * PLL handling cleanup * Add PLL comments * Keep only high fan-out BUFG * Add skeleton for tests * Utilize move_ram_o * GPIO wip * GPIO wip * PLL fixes * cleanup * FF_OBF support * Handle FF_IBF * Make SLEW FAST if not defined as in latest p_r * Make sure FF_OBF only driving GPIO * Moved pll calc into separate file * IDDR handling and started ODDR * Route DDR input for CC_ODDR * Notify error in case ODDR or IDDR are used but not with I/O pin * cleanup for CC_USR_RSTN * Extract proper RAM location for bitstream * Code cleanup * Allow auto place of pads * Use clock source flag * Configure GPIO clock signals * Handle conflicting clk * Use BUGF in proper order * Connected CLK, works without but good for debugging * CC_CFG_CTRL placement * Group RAM data 40 bytes per row * Write BRAM content * RAM wip * Use relative constraints from chipdb * fix broken build * Memory wip * Handle custom clock for memories * Support FIFO * optimize move_ram_io * Fix SR signal handling acorrding to findings * set placer beta * Pre place what we can * Revert "debug print if route found with wrong polarity" This reverts commit cf9ded2f183db0f4e85da454e5d9f2a4da3f5cfe. * Revert "Constrain routes to have correct inversion state" This reverts commit 795c284d4856ff17e37d64f013775e86f1bed803. * Remove virtual pips * Implement post processing inversion * ADDF add ability to route additional CO * Merge two ADDFs in one CPE * Added TODO * clangformat * Cleanup * Add serdes handling in config file * Cleanup * Cleanup * Cleanup * Fix in PLL handling * Fixed ADDF edge case * No need for this * Fix latch * Sanity checks * Support CC_BRAM_20K merge * Start creating testing environment * LVDS fixes * Add connection helper * Cleanup * Fix tabs * Formatting fix * Remove optimization tests for now * remove read_bitstream * removed .c_str() * Removed config parsing * using snake_case * Use bool_or_default where applicable * refactored bitstream write code * Add allow-unconstrained option * Update DFF related messages * Add clock constraint propagation --------- Co-authored-by: Lofty <dan.ravensloft@gmail.com>
2025-04-22 16:41:01 +02:00
X(RAM_I1)
X(RAM_I2)
X(RAM_O1)
X(RAM_O2)
X(C_RAM_I)
X(C_RAM_O)
gatemate: Initial SERDES support (#1476) * Initial SERDES support * use static array for default values * Split pack into multiple files * Pre-place BUFG and related cells
2025-05-06 15:56:26 +02:00
// RAM
Gatemate FPGA initial support (#1473) * Initial code for GateMate * Initial work on forming bitstream * Add CCF parsing * Use CCF to set IO location * Propagate errors * Restructure code * Add support for reading from config * Start adding infrastructure for reading bitstream * Fix script * GPIO initial work * Add IN1->RAM_O2 propagation * Fixed typo * Cleanup * More parameter checks * Add LVDS support * Cleanup * Keep just used connections for now * Naive lut tree CPE pack * Naive pack CC_DFF * pack DFF fixes * Handle MUX flags * Fix DFF pack * Prevent pass trough issues * Cleanup * Use device wrapper class * Update due to API changes * Use pin connection aliases * Start work on BUFG support * Fix CC_L2T5 pack * Add CPE input inverters * Constrain routes to have correct inversion state * Add clock inversion pip * Added MX2 and MX4 support * Fix script * BUFG support * debug print if route found with wrong polarity * Some CC_DFF improvements * Create reproducible chip database * Simplify inversion of special signals * Few more DFF features * Add forgotten virtual port renames * Handle muxes with constant inputs * Allow inversion for muxes * cleanup * DFF input can be constant * init DFF only when needed * cleanup * Add basic PLL support * Add some timings * Add USR_RSTN support * Display few more primitives * Use pass trough signals to validate architecture data * Use extra tile information from chip database * Updates needed for a build system changes * Implement SB_DRIVE support * Properly named configuration bits * autogenerated constids.inc * small fix * Initial code for CPE halfs * Some cleanup * make sure FFs are compatible * reverted due to db change * Merge DFF where applicable * memory allocation issue * fix * better MX2 * ram_i handling * Cleanup MX4 * Support latches * compare L_D flag as well * Move virtual pips * Naive addf pack * carry chains grouping * Keep chip database reproducible * split addf vectors * Block CPEs when GPIO is used * Prepare placement code * RAM_I/RAM_O rewrite * fix ram_i/o index * Display RAM and add new primitives * PLL wip code * CC_PLL_ADV packing * PLL handling cleanup * Add PLL comments * Keep only high fan-out BUFG * Add skeleton for tests * Utilize move_ram_o * GPIO wip * GPIO wip * PLL fixes * cleanup * FF_OBF support * Handle FF_IBF * Make SLEW FAST if not defined as in latest p_r * Make sure FF_OBF only driving GPIO * Moved pll calc into separate file * IDDR handling and started ODDR * Route DDR input for CC_ODDR * Notify error in case ODDR or IDDR are used but not with I/O pin * cleanup for CC_USR_RSTN * Extract proper RAM location for bitstream * Code cleanup * Allow auto place of pads * Use clock source flag * Configure GPIO clock signals * Handle conflicting clk * Use BUGF in proper order * Connected CLK, works without but good for debugging * CC_CFG_CTRL placement * Group RAM data 40 bytes per row * Write BRAM content * RAM wip * Use relative constraints from chipdb * fix broken build * Memory wip * Handle custom clock for memories * Support FIFO * optimize move_ram_io * Fix SR signal handling acorrding to findings * set placer beta * Pre place what we can * Revert "debug print if route found with wrong polarity" This reverts commit cf9ded2f183db0f4e85da454e5d9f2a4da3f5cfe. * Revert "Constrain routes to have correct inversion state" This reverts commit 795c284d4856ff17e37d64f013775e86f1bed803. * Remove virtual pips * Implement post processing inversion * ADDF add ability to route additional CO * Merge two ADDFs in one CPE * Added TODO * clangformat * Cleanup * Add serdes handling in config file * Cleanup * Cleanup * Cleanup * Fix in PLL handling * Fixed ADDF edge case * No need for this * Fix latch * Sanity checks * Support CC_BRAM_20K merge * Start creating testing environment * LVDS fixes * Add connection helper * Cleanup * Fix tabs * Formatting fix * Remove optimization tests for now * remove read_bitstream * removed .c_str() * Removed config parsing * using snake_case * Use bool_or_default where applicable * refactored bitstream write code * Add allow-unconstrained option * Update DFF related messages * Add clock constraint propagation --------- Co-authored-by: Lofty <dan.ravensloft@gmail.com>
2025-04-22 16:41:01 +02:00
X(RAM_cfg_forward_a_addr)
X(RAM_cfg_forward_b_addr)
X(RAM_cfg_forward_a0_clk)
X(RAM_cfg_forward_a0_en)
X(RAM_cfg_forward_a0_we)
X(RAM_cfg_forward_a1_clk)
X(RAM_cfg_forward_a1_en)
X(RAM_cfg_forward_a1_we)
X(RAM_cfg_forward_b0_clk)
X(RAM_cfg_forward_b0_en)
X(RAM_cfg_forward_b0_we)
X(RAM_cfg_forward_b1_clk)
X(RAM_cfg_forward_b1_en)
X(RAM_cfg_forward_b1_we)
X(RAM_cfg_sram_mode)
X(RAM_cfg_input_config_a0)
X(RAM_cfg_input_config_a1)
X(RAM_cfg_input_config_b0)
X(RAM_cfg_input_config_b1)
X(RAM_cfg_output_config_a0)
X(RAM_cfg_output_config_a1)
X(RAM_cfg_output_config_b0)
X(RAM_cfg_output_config_b1)
X(RAM_cfg_a0_writemode)
X(RAM_cfg_a1_writemode)
X(RAM_cfg_b0_writemode)
X(RAM_cfg_b1_writemode)
X(RAM_cfg_a0_set_outputreg)
X(RAM_cfg_a1_set_outputreg)
X(RAM_cfg_b0_set_outputreg)
X(RAM_cfg_b1_set_outputreg)
X(RAM_cfg_inversion_a0)
X(RAM_cfg_inversion_a1)
X(RAM_cfg_inversion_b0)
X(RAM_cfg_inversion_b1)
X(RAM_cfg_ecc_enable)
X(RAM_cfg_dyn_stat_select)
X(RAM_cfg_fifo_sync_enable)
X(RAM_cfg_almost_empty_offset)
X(RAM_cfg_fifo_async_enable)
X(RAM_cfg_almost_full_offset)
X(RAM_cfg_sram_delay)
X(RAM_cfg_datbm_sel)
X(RAM_cfg_cascade_enable)
gatemate: Initial SERDES support (#1476) * Initial SERDES support * use static array for default values * Split pack into multiple files * Pre-place BUFG and related cells
2025-05-06 15:56:26 +02:00
// SERDES - param is split
X(RX_EN_EQA_EXT_VALUE_0)
X(RX_EN_EQA_EXT_VALUE_1)
X(RX_EN_EQA_EXT_VALUE_2)
X(RX_EN_EQA_EXT_VALUE_3)
// SERDES - read-only params
X(RX_CALIB_DONE)
X(RX_CALIB_CAL)
X(RX_EQA_LOCKED)
X(RX_EQA_TAPW)
X(RX_TH_MON)
X(RX_OFFSET)
X(RX_CDR_LOCKED)
X(RX_CDR_FREQ_ACC_VAL)
X(RX_CDR_PHASE_ACC_VAL)
X(RX_EYE_MEAS_CORRECT_11S)
X(RX_EYE_MEAS_WRONG_11S)
X(RX_EYE_MEAS_CORRECT_00S)
X(RX_EYE_MEAS_WRONG_00S)
X(RX_EYE_MEAS_CORRECT_001S)
X(RX_EYE_MEAS_WRONG_001S)
X(RX_EYE_MEAS_CORRECT_110S)
X(RX_EYE_MEAS_WRONG_110S)
X(RX_EI_EN)
X(RX_PRBS_ERR_CNT)
X(RX_PRBS_LOCKED)
X(RX_DATA)
X(RX_PRESENT)
X(RX_DETECT_DONE)
X(RX_BUF_ERR)
X(RX_BYTE_IS_ALIGNED)
X(RX_RESET_DONE)
X(TX_CALIB_DONE)
X(TX_CALIB_CAL)
X(TX_CM_SAR_RESULT_0)
X(TX_CM_SAR_RESULT_1)
X(TX_BUF_ERR)
X(TX_RESET_DONE)
X(TX_DATA)
X(PLL_LOCKED)
X(PLL_CAP_FT_OF)
X(PLL_CAP_FT_UF)
X(PLL_CAP_FT)
X(PLL_CAP_STATE)
X(PLL_SYNC_VALUE)
X(PLL_BISC_TIMER_DONE)
X(PLL_BISC_CP)
X(PLL_BISC_CO)
Gatemate FPGA initial support (#1473) * Initial code for GateMate * Initial work on forming bitstream * Add CCF parsing * Use CCF to set IO location * Propagate errors * Restructure code * Add support for reading from config * Start adding infrastructure for reading bitstream * Fix script * GPIO initial work * Add IN1->RAM_O2 propagation * Fixed typo * Cleanup * More parameter checks * Add LVDS support * Cleanup * Keep just used connections for now * Naive lut tree CPE pack * Naive pack CC_DFF * pack DFF fixes * Handle MUX flags * Fix DFF pack * Prevent pass trough issues * Cleanup * Use device wrapper class * Update due to API changes * Use pin connection aliases * Start work on BUFG support * Fix CC_L2T5 pack * Add CPE input inverters * Constrain routes to have correct inversion state * Add clock inversion pip * Added MX2 and MX4 support * Fix script * BUFG support * debug print if route found with wrong polarity * Some CC_DFF improvements * Create reproducible chip database * Simplify inversion of special signals * Few more DFF features * Add forgotten virtual port renames * Handle muxes with constant inputs * Allow inversion for muxes * cleanup * DFF input can be constant * init DFF only when needed * cleanup * Add basic PLL support * Add some timings * Add USR_RSTN support * Display few more primitives * Use pass trough signals to validate architecture data * Use extra tile information from chip database * Updates needed for a build system changes * Implement SB_DRIVE support * Properly named configuration bits * autogenerated constids.inc * small fix * Initial code for CPE halfs * Some cleanup * make sure FFs are compatible * reverted due to db change * Merge DFF where applicable * memory allocation issue * fix * better MX2 * ram_i handling * Cleanup MX4 * Support latches * compare L_D flag as well * Move virtual pips * Naive addf pack * carry chains grouping * Keep chip database reproducible * split addf vectors * Block CPEs when GPIO is used * Prepare placement code * RAM_I/RAM_O rewrite * fix ram_i/o index * Display RAM and add new primitives * PLL wip code * CC_PLL_ADV packing * PLL handling cleanup * Add PLL comments * Keep only high fan-out BUFG * Add skeleton for tests * Utilize move_ram_o * GPIO wip * GPIO wip * PLL fixes * cleanup * FF_OBF support * Handle FF_IBF * Make SLEW FAST if not defined as in latest p_r * Make sure FF_OBF only driving GPIO * Moved pll calc into separate file * IDDR handling and started ODDR * Route DDR input for CC_ODDR * Notify error in case ODDR or IDDR are used but not with I/O pin * cleanup for CC_USR_RSTN * Extract proper RAM location for bitstream * Code cleanup * Allow auto place of pads * Use clock source flag * Configure GPIO clock signals * Handle conflicting clk * Use BUGF in proper order * Connected CLK, works without but good for debugging * CC_CFG_CTRL placement * Group RAM data 40 bytes per row * Write BRAM content * RAM wip * Use relative constraints from chipdb * fix broken build * Memory wip * Handle custom clock for memories * Support FIFO * optimize move_ram_io * Fix SR signal handling acorrding to findings * set placer beta * Pre place what we can * Revert "debug print if route found with wrong polarity" This reverts commit cf9ded2f183db0f4e85da454e5d9f2a4da3f5cfe. * Revert "Constrain routes to have correct inversion state" This reverts commit 795c284d4856ff17e37d64f013775e86f1bed803. * Remove virtual pips * Implement post processing inversion * ADDF add ability to route additional CO * Merge two ADDFs in one CPE * Added TODO * clangformat * Cleanup * Add serdes handling in config file * Cleanup * Cleanup * Cleanup * Fix in PLL handling * Fixed ADDF edge case * No need for this * Fix latch * Sanity checks * Support CC_BRAM_20K merge * Start creating testing environment * LVDS fixes * Add connection helper * Cleanup * Fix tabs * Formatting fix * Remove optimization tests for now * remove read_bitstream * removed .c_str() * Removed config parsing * using snake_case * Use bool_or_default where applicable * refactored bitstream write code * Add allow-unconstrained option * Update DFF related messages * Add clock constraint propagation --------- Co-authored-by: Lofty <dan.ravensloft@gmail.com>
2025-04-22 16:41:01 +02:00
X(CC_ADDF2)
X(A2)
X(B2)
gatemate: Multi die support and primitives model improvement (#1501) * SER_CLK support * Update constids * wip * CLK_FEEDBACK * Handle SER_CLK and SER_CLK_N * clangformat * Cleanup * Use _ as separator for PLL CFGs * Remove unused clocking cells * Do not use same name for IO models * Fix IDDR merge * Cleanup * Properly handle user global signals * Move signal inversion in bitstream creation * Start adding multi die support * Display die location for pins used * Do not use constant s as locations * Cleanup SB_DRIVE handling * Use DDR locations from chip database * Place only in prefered die for now * Set D2D * Fixed typos
2025-06-18 08:32:57 +02:00
X(CPE_IBUF)
X(CPE_OBUF)
X(CPE_TOBUF)
X(CPE_IOBUF)
X(CPE_LVDS_IBUF)
X(CPE_LVDS_OBUF)
X(CPE_LVDS_TOBUF)
X(CPE_LVDS_IOBUF)
Use improved CPE model (#1503) * CPE mapping improvements * Use CP_OUT for adders * Fixes * Small fixes * Cleanups * Cleanup * Cleanups * Fixes * Fixes * Optimize * Cleanup * clangformat * Cleanup * Cleanup * Bump required version of database * Cleanup * Resolve name conflicts * Fix signal routing * Make CPE_LATCH separate * Add more timings models, need updated values * Fixed warning * multiplier support from lofty/gatemate-mult * explicitly zero some params in B passthrough * comment the relevant CPE inputs in check_multipliers * Rename some of bels * remove _lower from name * refactor multiplier checking * Revert "remove _lower from name" This reverts commit daa1041bdf855b664c8f6462e1ed994459239b9c. * Fixe net name to be unique * Make sure we at least generate bitstream with all info * Simplify zero * Bounded cell type in gui * typo fix * Remove A passthrough inversion option * Clean up CarryGenCell config * Update a passthru to use new primitives * Cleanup for adders * Clean up MsbRoutingCell * Cleanup * Refactor A connection code * Make it more as in PR #1513 * Added cplines to bpassthru and fixed constant driver for A * Add parts * Added comp out connections * clangformat * clangformat * Clean up B passthrough connections * wire up a bunch of intermediate signals * Bit of cleanup * handing of C_EN_IN * C_EN_CIN fixes * connect f_route to its lines * fix cite for FRoutingCell * fixup, oops * connect multfab to its lines * Commented line * Connect CPOUTs * Handle C_I params * connect CINY1 for CarryGenCell * fix carry gen CINX * Update L2T4 model * Updates for ADDCIN * clangformat * fix some issues with multfab and f_route * look at C_I when doing inversion * Only set some C_I signals when used * Fix one more place * do not use cplines so we can merge in one cell * Cover cases that could be optimized out * clangformat * Cleanups * Disable multiplier usage for now --------- Co-authored-by: Lofty <dan.ravensloft@gmail.com>
2025-07-07 10:14:48 +02:00
X(CPE_L2T4)
X(CPE_ADDF)
X(CPE_ADDF2)
X(CPE_MULT)
X(CPE_MX4)
//X(CPE_EN_CIN)
X(CPE_CONCAT)
//X(CPE_ADDCIN)
X(CPE_DUMMY)
X(CPE_LATCH)
X(L2T4_UPPER)
X(CPE_MX8)
X(CPE_BRIDGE)
Add MULT_INVERT property
2025-08-01 17:46:43 +02:00
X(MULT_INVERT)
gatemate: Enable placing RAM halfs (#1544) * gatemate: Split BRAMs into halfs * Cleanups * move code arround * optmize remapping halfs * Name RAM cells * fix cluster setting for cascade mode * attach ECC pins * rewire global clocks * bump chip database version * Fix KEEPER setting * Fix conflict check * cleanup
2025-09-02 08:03:22 +02:00
X(RAM_HALF)
X(RAM_HALF_DUMMY)
gatemate: add iopath delays (#1537) * Timing * clangformat * Import some new data * Import all timing data * Add constants for needed timings * Add separate file for delay handling * wip * Added helpers * wip * proper place for assignArchInfo * wip * wip * Fixes for IO * Add IOSEL delays * Fix logic loops * help figure out some ram paths * return true only if exists * cover all primitives * Disable not used paths * clockToQ * Added some RAM timings * Add more IOPATHs * cleanup * cleanup * Map few more timings * remove short name options * support strings as options * no need for return
2025-08-22 11:07:34 +02:00
// Timing
X(timing_ADDF2x_IN5_8_comb2)
X(timing_CIN_C_CINI)
X(timing_CIN_C_IN4)
X(timing_CINX_IN4)
X(timing__ARBLUT_CINX_OUT1)
X(timing__ARBLUT_CINX_OUT2)
X(timing_CPOUT_cpout)
X(timing_LUT2A_LUT2B)
X(timing_PINX_IN8)
X(timing__ARBLUT_PINX_OUT1)
X(timing__ARBLUT_PINX_OUT2)
X(timing_PINY1_IN2_6)
X(timing__ARBLUT_PINY1_OUT1)
X(timing__ARBLUT_PINY1_OUT2)
X(timing_Q1_OUT1)
X(timing_Q2_OUT2)
X(timing_RAM_ECC_IOPATH_1)
X(timing_RAM_ECC_IOPATH_2)
X(timing_RAM_ECC_IOPATH_3)
X(timing_RAM_ECC_IOPATH_4)
X(timing_RAM_ECC_SETUPHOLD_1)
X(timing_RAM_ECC_SETUPHOLD_10)
X(timing_RAM_ECC_SETUPHOLD_2)
X(timing_RAM_ECC_SETUPHOLD_3)
X(timing_RAM_ECC_SETUPHOLD_4)
X(timing_RAM_ECC_SETUPHOLD_5)
X(timing_RAM_ECC_SETUPHOLD_6)
X(timing_RAM_ECC_SETUPHOLD_7)
X(timing_RAM_ECC_SETUPHOLD_8)
X(timing_RAM_ECC_SETUPHOLD_9)
X(timing_RAM_ECC_WIDTH)
X(timing_RAM_NOECC_IOPATH_1)
X(timing_RAM_NOECC_IOPATH_2)
X(timing_RAM_NOECC_IOPATH_3)
X(timing_RAM_NOECC_IOPATH_4)
X(timing_RAM_NOECC_SETUPHOLD_1)
X(timing_RAM_NOECC_SETUPHOLD_10)
X(timing_RAM_NOECC_SETUPHOLD_2)
X(timing_RAM_NOECC_SETUPHOLD_3)
X(timing_RAM_NOECC_SETUPHOLD_4)
X(timing_RAM_NOECC_SETUPHOLD_5)
X(timing_RAM_NOECC_SETUPHOLD_6)
X(timing_RAM_NOECC_SETUPHOLD_7)
X(timing_RAM_NOECC_SETUPHOLD_8)
X(timing_RAM_NOECC_SETUPHOLD_9)
X(timing_RAM_NOECC_WIDTH)
X(timing_RAM_REG_IOPATH_1)
X(timing_RAM_REG_IOPATH_2)
X(timing_RAM_REG_IOPATH_3)
X(timing_RAM_REG_IOPATH_4)
X(timing_RAM_REG_SETUPHOLD_1)
X(timing_RAM_REG_SETUPHOLD_10)
X(timing_RAM_REG_SETUPHOLD_2)
X(timing_RAM_REG_SETUPHOLD_3)
X(timing_RAM_REG_SETUPHOLD_4)
X(timing_RAM_REG_SETUPHOLD_5)
X(timing_RAM_REG_SETUPHOLD_6)
X(timing_RAM_REG_SETUPHOLD_7)
X(timing_RAM_REG_SETUPHOLD_8)
X(timing_RAM_REG_SETUPHOLD_9)
X(timing_RAM_REG_WIDTH)
X(timing__ADDF2X_CINX_COUTX)
X(timing__ADDF2X_IN1_COUTX)
X(timing__ADDF2X_IN1_OUT1)
X(timing__ADDF2X_IN1_OUT2)
X(timing__ADDF2X_IN1_RAM_O1)
X(timing__ADDF2X_IN1_RAM_O2)
X(timing__ADDF2X_IN2_COUTX)
X(timing__ADDF2X_IN2_OUT1)
X(timing__ADDF2X_IN2_OUT2)
X(timing__ADDF2X_IN2_RAM_O1)
X(timing__ADDF2X_IN2_RAM_O2)
X(timing__ADDF2X_IN3_COUTX)
X(timing__ADDF2X_IN3_OUT1)
X(timing__ADDF2X_IN3_OUT2)
X(timing__ADDF2X_IN3_RAM_O1)
X(timing__ADDF2X_IN3_RAM_O2)
X(timing__ADDF2X_IN4_COUTX)
X(timing__ADDF2X_IN4_OUT1)
X(timing__ADDF2X_IN4_OUT2)
X(timing__ADDF2X_IN4_RAM_O1)
X(timing__ADDF2X_IN4_RAM_O2)
X(timing__ADDF2X_IN5_COUTX)
X(timing__ADDF2X_IN5_OUT1)
X(timing__ADDF2X_IN5_OUT2)
X(timing__ADDF2X_IN5_RAM_O1)
X(timing__ADDF2X_IN5_RAM_O2)
X(timing__ADDF2X_IN6_COUTX)
X(timing__ADDF2X_IN6_OUT1)
X(timing__ADDF2X_IN6_OUT2)
X(timing__ADDF2X_IN6_RAM_O1)
X(timing__ADDF2X_IN6_RAM_O2)
X(timing__ADDF2X_IN7_COUTX)
X(timing__ADDF2X_IN7_OUT1)
X(timing__ADDF2X_IN7_OUT2)
X(timing__ADDF2X_IN7_RAM_O1)
X(timing__ADDF2X_IN7_RAM_O2)
X(timing__ADDF2X_IN8_COUTX)
X(timing__ADDF2X_IN8_OUT1)
X(timing__ADDF2X_IN8_OUT2)
X(timing__ADDF2X_IN8_RAM_O1)
X(timing__ADDF2X_IN8_RAM_O2)
X(timing__ADDF2Y1_CINY1_COUTY)
X(timing__ADDF2Y1_CINY1_OUT1)
X(timing__ADDF2Y1_CINY1_OUT2)
X(timing__ADDF2Y1_IN1_COUTY1)
X(timing__ADDF2Y1_IN1_OUT1)
X(timing__ADDF2Y1_IN1_OUT2)
X(timing__ADDF2Y1_IN1_RAM_O1)
X(timing__ADDF2Y1_IN1_RAM_O2)
X(timing__ADDF2Y1_IN2_COUTY1)
X(timing__ADDF2Y1_IN2_OUT1)
X(timing__ADDF2Y1_IN2_OUT2)
X(timing__ADDF2Y1_IN2_RAM_O1)
X(timing__ADDF2Y1_IN2_RAM_O2)
X(timing__ADDF2Y1_IN3_COUTY1)
X(timing__ADDF2Y1_IN3_OUT1)
X(timing__ADDF2Y1_IN3_OUT2)
X(timing__ADDF2Y1_IN3_RAM_O1)
X(timing__ADDF2Y1_IN3_RAM_O2)
X(timing__ADDF2Y1_IN4_COUTY1)
X(timing__ADDF2Y1_IN4_OUT1)
X(timing__ADDF2Y1_IN4_OUT2)
X(timing__ADDF2Y1_IN4_RAM_O1)
X(timing__ADDF2Y1_IN4_RAM_O2)
X(timing__ADDF2Y1_IN5_COUTY1)
X(timing__ADDF2Y1_IN5_OUT1)
X(timing__ADDF2Y1_IN5_OUT2)
X(timing__ADDF2Y1_IN5_RAM_O1)
X(timing__ADDF2Y1_IN5_RAM_O2)
X(timing__ADDF2Y1_IN6_COUTY1)
X(timing__ADDF2Y1_IN6_OUT1)
X(timing__ADDF2Y1_IN6_OUT2)
X(timing__ADDF2Y1_IN6_RAM_O1)
X(timing__ADDF2Y1_IN6_RAM_O2)
X(timing__ADDF2Y1_IN7_COUTY1)
X(timing__ADDF2Y1_IN7_OUT1)
X(timing__ADDF2Y1_IN7_OUT2)
X(timing__ADDF2Y1_IN7_RAM_O1)
X(timing__ADDF2Y1_IN7_RAM_O2)
X(timing__ADDF2Y1_IN8_COUTY1)
X(timing__ADDF2Y1_IN8_OUT1)
X(timing__ADDF2Y1_IN8_OUT2)
X(timing__ADDF2Y1_IN8_RAM_O1)
X(timing__ADDF2Y1_IN8_RAM_O2)
X(timing__ARBLUT_IN1_OUT1)
X(timing__ARBLUT_IN1_OUT2)
X(timing__ARBLUT_IN1_RAM_O1)
X(timing__ARBLUT_IN1_RAM_O2)
X(timing__ARBLUT_IN2_OUT1)
X(timing__ARBLUT_IN2_OUT2)
X(timing__ARBLUT_IN2_RAM_O1)
X(timing__ARBLUT_IN2_RAM_O2)
X(timing__ARBLUT_IN3_OUT1)
X(timing__ARBLUT_IN3_OUT2)
X(timing__ARBLUT_IN3_RAM_O1)
X(timing__ARBLUT_IN3_RAM_O2)
X(timing__ARBLUT_IN4_OUT1)
X(timing__ARBLUT_IN4_OUT2)
X(timing__ARBLUT_IN4_RAM_O1)
X(timing__ARBLUT_IN4_RAM_O2)
X(timing__ARBLUT_IN5_OUT1)
X(timing__ARBLUT_IN5_RAM_O1)
X(timing__ARBLUT_IN5_RAM_O2)
X(timing__ARBLUT_IN6_OUT1)
X(timing__ARBLUT_IN6_RAM_O1)
X(timing__ARBLUT_IN6_RAM_O2)
X(timing__ARBLUT_IN7_OUT1)
X(timing__ARBLUT_IN7_RAM_O1)
X(timing__ARBLUT_IN7_RAM_O2)
X(timing__ARBLUT_IN8_OUT1)
X(timing__ARBLUT_IN8_RAM_O1)
X(timing__ARBLUT_IN8_RAM_O2)
X(timing__ARBLUT_RAM_I1_COUTX)
X(timing__ARBLUT_RAM_I1_OUT1)
X(timing__ARBLUT_RAM_I1_POUTX)
X(timing__ARBLUT_RAM_I2_OUT2)
X(timing__ARBLUT_RAM_I2_POUTX)
X(timing__ARBLUT_RAM_O____RAM)
X(timing__MULT_CINX_COUTX)
X(timing__MULT_CINX_COUTY1)
X(timing__MULT_CINX_COUTY2)
X(timing__MULT_CINY1_COUTX)
X(timing__MULT_CINY1_COUTY1)
X(timing__MULT_CINY1_COUTY2)
X(timing__MULT_CINY1_POUTX)
X(timing__MULT_CINY2_COUTX)
X(timing__MULT_CINY2_COUTY2)
X(timing__MULT_CINY2_POUTX)
X(timing__MULT_IN1_COUTX)
X(timing__MULT_IN1_COUTY1)
X(timing__MULT_IN1_COUTY2)
X(timing__MULT_IN1_RAM_O1)
X(timing__MULT_IN1_RAM_O2)
X(timing__MULT_IN2_RAM_O1)
X(timing__MULT_IN2_RAM_O2)
X(timing__MULT_IN3_RAM_O1)
X(timing__MULT_IN3_RAM_O2)
X(timing__MULT_IN4_RAM_O1)
X(timing__MULT_IN4_RAM_O2)
X(timing__MULT_IN5_COUTX)
X(timing__MULT_IN5_COUTY1)
X(timing__MULT_IN5_COUTY2)
X(timing__MULT_IN5_POUTX)
X(timing__MULT_IN5_RAM_O1)
X(timing__MULT_IN5_RAM_O2)
X(timing__MULT_IN6_RAM_O1)
X(timing__MULT_IN6_RAM_O2)
X(timing__MULT_IN7_RAM_O1)
X(timing__MULT_IN7_RAM_O2)
X(timing__MULT_IN8_COUTX)
X(timing__MULT_IN8_COUTY2)
X(timing__MULT_IN8_POUTX)
X(timing__MULT_IN8_RAM_O1)
X(timing__MULT_IN8_RAM_O2)
X(timing__MULT_PINX_COUTX)
X(timing__MULT_PINX_COUTY1)
X(timing__MULT_PINX_COUTY2)
X(timing__MULT_PINX_POUTX)
X(timing__MULT_PINY1_COUTX)
X(timing__MULT_PINY1_COUTY1)
X(timing__MULT_PINY1_COUTY2)
X(timing__MULT_PINY1_POUTX)
X(timing__MULT_PINY1_POUTY1)
X(timing__MULT_PINY2_COUTX)
X(timing__MULT_PINY2_COUTY2)
X(timing__MULT_PINY2_POUTX)
X(timing__MULT_PINY2_POUTY2)
X(timing__MX4A_IN1_OUT1)
X(timing__MX4A_IN1_RAM_O1)
X(timing__MX4A_IN1_RAM_O2)
X(timing__MX4A_IN2_OUT1)
X(timing__MX4A_IN2_RAM_O1)
X(timing__MX4A_IN2_RAM_O2)
X(timing__MX4A_IN3_OUT1)
X(timing__MX4A_IN3_RAM_O1)
X(timing__MX4A_IN3_RAM_O2)
X(timing__MX4A_IN4_OUT1)
X(timing__MX4A_IN4_RAM_O1)
X(timing__MX4A_IN4_RAM_O2)
X(timing__MX4A_IN5_OUT1)
X(timing__MX4A_IN5_RAM_O1)
X(timing__MX4A_IN5_RAM_O2)
X(timing__MX4A_IN6_OUT1)
X(timing__MX4A_IN6_RAM_O1)
X(timing__MX4A_IN6_RAM_O2)
X(timing__MX4A_IN7_OUT1)
X(timing__MX4A_IN7_RAM_O1)
X(timing__MX4A_IN7_RAM_O2)
X(timing__MX4A_IN8_OUT1)
X(timing__MX4A_IN8_RAM_O1)
X(timing__MX4A_IN8_RAM_O2)
X(timing__MX4B_IN1_OUT1)
X(timing__MX4B_IN1_OUT2)
X(timing__MX4B_IN1_RAM_O1)
X(timing__MX4B_IN1_RAM_O2)
X(timing__MX4B_IN2_OUT1)
X(timing__MX4B_IN2_OUT2)
X(timing__MX4B_IN2_RAM_O1)
X(timing__MX4B_IN2_RAM_O2)
X(timing__MX4B_IN3_OUT1)
X(timing__MX4B_IN3_OUT2)
X(timing__MX4B_IN3_RAM_O1)
X(timing__MX4B_IN3_RAM_O2)
X(timing__MX4B_IN4_OUT1)
X(timing__MX4B_IN4_OUT2)
X(timing__MX4B_IN4_RAM_O1)
X(timing__MX4B_IN4_RAM_O2)
X(timing__MX4B_IN5_OUT1)
X(timing__MX4B_IN5_OUT2)
X(timing__MX4B_IN5_RAM_O1)
X(timing__MX4B_IN5_RAM_O2)
X(timing__MX4B_IN6_OUT1)
X(timing__MX4B_IN6_OUT2)
X(timing__MX4B_IN6_RAM_O1)
X(timing__MX4B_IN6_RAM_O2)
X(timing__MX4B_IN7_OUT1)
X(timing__MX4B_IN7_OUT2)
X(timing__MX4B_IN7_RAM_O1)
X(timing__MX4B_IN7_RAM_O2)
X(timing__MX4B_IN8_OUT1)
X(timing__MX4B_IN8_OUT2)
X(timing__MX4B_IN8_RAM_O1)
X(timing__MX4B_IN8_RAM_O2)
X(timing__MX8_CLK_OUT1)
X(timing__MX8_CLK_OUT2)
X(timing__MX8_EN_OUT1)
X(timing__MX8_EN_OUT2)
X(timing__MX8_IN1_OUT1)
X(timing__MX8_IN1_OUT2)
X(timing__MX8_IN1_RAM_O1)
X(timing__MX8_IN1_RAM_O2)
X(timing__MX8_IN2_OUT1)
X(timing__MX8_IN2_OUT2)
X(timing__MX8_IN2_RAM_O1)
X(timing__MX8_IN2_RAM_O2)
X(timing__MX8_IN3_OUT1)
X(timing__MX8_IN3_OUT2)
X(timing__MX8_IN3_RAM_O1)
X(timing__MX8_IN3_RAM_O2)
X(timing__MX8_IN4_OUT1)
X(timing__MX8_IN4_OUT2)
X(timing__MX8_IN4_RAM_O1)
X(timing__MX8_IN4_RAM_O2)
X(timing__MX8_IN5_OUT1)
X(timing__MX8_IN5_OUT2)
X(timing__MX8_IN5_RAM_O1)
X(timing__MX8_IN5_RAM_O2)
X(timing__MX8_IN6_OUT1)
X(timing__MX8_IN6_OUT2)
X(timing__MX8_IN6_RAM_O1)
X(timing__MX8_IN6_RAM_O2)
X(timing__MX8_IN7_OUT1)
X(timing__MX8_IN7_OUT2)
X(timing__MX8_IN7_RAM_O1)
X(timing__MX8_IN7_RAM_O2)
X(timing__MX8_IN8_OUT1)
X(timing__MX8_IN8_OUT2)
X(timing__MX8_IN8_RAM_O1)
X(timing__MX8_IN8_RAM_O2)
X(timing__MX8_SR_OUT1)
X(timing__MX8_SR_OUT2)
X(timing__ROUTING_CINX_COUTX)
X(timing__ROUTING_CINX_COUTY1)
X(timing__ROUTING_CINX_COUTY2)
X(timing__ROUTING_CINX_POUTX)
X(timing__ROUTING_CINX_POUTY1)
X(timing__ROUTING_CINX_POUTY2)
X(timing__ROUTING_CINY1_COUTX)
X(timing__ROUTING_CINY1_COUTY)
X(timing__ROUTING_CINY1_POUTX)
X(timing__ROUTING_CINY1_POUTY)
X(timing__ROUTING_CINY2_COUTX)
X(timing__ROUTING_CINY2_COUTY)
X(timing__ROUTING_IN1_RAM_O1)
X(timing__ROUTING_IN1_RAM_O2)
X(timing__ROUTING_IN2_RAM_O1)
X(timing__ROUTING_IN2_RAM_O2)
X(timing__ROUTING_IN3_RAM_O1)
X(timing__ROUTING_IN3_RAM_O2)
X(timing__ROUTING_IN4_RAM_O1)
X(timing__ROUTING_IN4_RAM_O2)
X(timing__ROUTING_IN5_RAM_O1)
X(timing__ROUTING_IN5_RAM_O2)
X(timing__ROUTING_IN6_RAM_O1)
X(timing__ROUTING_IN6_RAM_O2)
X(timing__ROUTING_IN7_RAM_O1)
X(timing__ROUTING_IN7_RAM_O2)
X(timing__ROUTING_IN8_RAM_O1)
X(timing__ROUTING_IN8_RAM_O2)
X(timing__ROUTING_PINX_COUTX)
X(timing__ROUTING_PINX_COUTY1)
X(timing__ROUTING_PINX_COUTY2)
X(timing__ROUTING_PINX_POUTX)
X(timing__ROUTING_PINX_POUTY1)
X(timing__ROUTING_PINX_POUTY2)
X(timing__ROUTING_PINY1_COUTX)
X(timing__ROUTING_PINY1_COUTY)
X(timing__ROUTING_PINY1_POUTX)
X(timing__ROUTING_PINY1_POUTY)
X(timing__ROUTING_PINY2_POUTY)
X(timing__SEQ_CINX_FF1_D)
X(timing__SEQ_CINX_FF2_D)
X(timing__SEQ_CINX_LH1_D)
X(timing__SEQ_CINX_LH2_D)
X(timing__SEQ_CINY1_FF1_D)
X(timing__SEQ_CINY1_FF2_D)
X(timing__SEQ_CINY1_LH1_D)
X(timing__SEQ_CINY1_LH2_D)
X(timing__SEQ_CINY2_FF1_Q)
X(timing__SEQ_CINY2_FF2_Q)
X(timing__SEQ_CINY2_LH1_Q)
X(timing__SEQ_CINY2_LH2_Q)
X(timing__SEQ_CLK_FF1_Q)
X(timing__SEQ_CLK_FF2_Q)
X(timing__SEQ_CLK_LH1_Q)
X(timing__SEQ_CLK_LH2_Q)
X(timing__SEQ_EN_FF1_EN)
X(timing__SEQ_EN_FF2_EN)
X(timing__SEQ_EN_LH1_EN)
X(timing__SEQ_EN_LH2_EN)
X(timing__SEQ_IN1_FF1_D)
X(timing__SEQ_IN1_FF2_D)
X(timing__SEQ_IN1_LH1_D)
X(timing__SEQ_IN1_LH2_D)
X(timing__SEQ_IN2_FF1_D)
X(timing__SEQ_IN2_FF2_D)
X(timing__SEQ_IN2_LH1_D)
X(timing__SEQ_IN2_LH2_D)
X(timing__SEQ_IN3_FF1_D)
X(timing__SEQ_IN3_FF2_D)
X(timing__SEQ_IN3_LH1_D)
X(timing__SEQ_IN3_LH2_D)
X(timing__SEQ_IN4_FF1_D)
X(timing__SEQ_IN4_FF2_D)
X(timing__SEQ_IN4_LH1_D)
X(timing__SEQ_IN4_LH2_D)
X(timing__SEQ_IN5_FF1_D)
X(timing__SEQ_IN5_FF2_D)
X(timing__SEQ_IN5_LH1_D)
X(timing__SEQ_IN5_LH2_D)
X(timing__SEQ_IN6_FF1_D)
X(timing__SEQ_IN6_FF2_D)
X(timing__SEQ_IN6_LH1_D)
X(timing__SEQ_IN6_LH2_D)
X(timing__SEQ_IN7_FF1_D)
X(timing__SEQ_IN7_FF2_D)
X(timing__SEQ_IN7_LH1_D)
X(timing__SEQ_IN7_LH2_D)
X(timing__SEQ_IN8_FF1_D)
X(timing__SEQ_IN8_FF2_D)
X(timing__SEQ_IN8_LH1_D)
X(timing__SEQ_IN8_LH2_D)
X(timing__SEQ_PINX_FF1_D)
X(timing__SEQ_PINX_FF2_D)
X(timing__SEQ_PINX_LH1_D)
X(timing__SEQ_PINX_LH2_D)
X(timing__SEQ_PINY1_FF1_D)
X(timing__SEQ_PINY1_FF2_D)
X(timing__SEQ_PINY1_LH1_D)
X(timing__SEQ_PINY1_LH2_D)
X(timing__SEQ_PINY2_FF1_EN)
X(timing__SEQ_PINY2_FF2_EN)
X(timing__SEQ_PINY2_LH1_EN)
X(timing__SEQ_PINY2_LH2_EN)
X(timing__SEQ_RAM_I1_FF1_D)
X(timing__SEQ_RAM_I1_FF2_D)
X(timing__SEQ_RAM_I1_LH1_D)
X(timing__SEQ_RAM_I1_LH2_D)
X(timing__SEQ_RAM_I2_FF1_D)
X(timing__SEQ_RAM_I2_FF2_D)
X(timing__SEQ_RAM_I2_LH1_D)
X(timing__SEQ_RAM_I2_LH2_D)
X(timing__SEQ_SR_FF1_SR)
X(timing__SEQ_SR_FF2_SR)
X(timing__SEQ_SR_LH1_SR)
X(timing__SEQ_SR_LH2_SR)
X(timing_clkin_CLK0_CLK_REF0)
X(timing_clkin_CLK0_CLK_REF1)
X(timing_clkin_CLK0_CLK_REF2)
X(timing_clkin_CLK0_CLK_REF3)
X(timing_clkin_CLK1_CLK_REF0)
X(timing_clkin_CLK1_CLK_REF1)
X(timing_clkin_CLK1_CLK_REF2)
X(timing_clkin_CLK1_CLK_REF3)
X(timing_clkin_CLK2_CLK_REF0)
X(timing_clkin_CLK2_CLK_REF1)
X(timing_clkin_CLK2_CLK_REF2)
X(timing_clkin_CLK2_CLK_REF3)
X(timing_clkin_CLK3_CLK_REF0)
X(timing_clkin_CLK3_CLK_REF1)
X(timing_clkin_CLK3_CLK_REF2)
X(timing_clkin_CLK3_CLK_REF3)
X(timing_clkin_JTAG_CLK_CLK_REF0)
X(timing_clkin_JTAG_CLK_CLK_REF1)
X(timing_clkin_JTAG_CLK_CLK_REF2)
X(timing_clkin_JTAG_CLK_CLK_REF3)
X(timing_clkin_SER_CLK_CLK_REF0)
X(timing_clkin_SER_CLK_CLK_REF1)
X(timing_clkin_SER_CLK_CLK_REF2)
X(timing_clkin_SER_CLK_CLK_REF3)
X(timing_clkin_SPI_CLK_CLK_REF0)
X(timing_clkin_SPI_CLK_CLK_REF1)
X(timing_clkin_SPI_CLK_CLK_REF2)
X(timing_clkin_SPI_CLK_CLK_REF3)
X(timing_comb12_COUTX)
X(timing_comb12_COUTY1)
X(timing_comb12_COUTY2)
X(timing_comb12_POUTX)
X(timing_comb12_POUTY1)
X(timing_comb12_POUTY2)
X(timing_comb12_RAM_O1)
X(timing_comb12_RAM_O2)
X(timing_comb12_compout_COUTX)
X(timing_comb12_compout_COUTY)
X(timing_comb12_compout_POUTX)
X(timing_comb12_compout_POUTY)
X(timing_comb1_D1)
X(timing_comb1_L1)
X(timing_comb1_OUT1)
X(timing_comb1_compout)
X(timing_comb2_D2)
X(timing_comb2_L2)
X(timing_comb2_OUT2)
X(timing_comb2_compout)
X(timing_cpout_OUT1)
X(timing_cpout_OUT2)
X(timing_del_CPE_CP_Q)
X(timing_del_CPE_D_Q)
X(timing_del_CPE_R_Q)
X(timing_del_CPE_S_Q)
X(timing_del_CP_carry_path)
X(timing_del_CP_clkin)
X(timing_del_CP_enin)
X(timing_del_CP_prop_path)
X(timing_del_GLBOUT_IO_SEL)
X(timing_del_GLBOUT_sb_big)
X(timing_del_Hold_D_L)
X(timing_del_Hold_RAM)
X(timing_del_Hold_RN_SN)
X(timing_del_Hold_SN_RN)
X(timing_del_IBF)
X(timing_del_IO_SEL_Q_in)
X(timing_del_IO_SEL_Q_out)
X(timing_del_LVDS_IBF)
X(timing_del_LVDS_OBF)
X(timing_del_LVDS_TOBF_ctrl)
X(timing_del_OBF)
X(timing_del_RAMO_xOBF)
X(timing_del_RAM_CLK_DO)
X(timing_del_Setup_D_L)
X(timing_del_Setup_RAM)
X(timing_del_Setup_RN_SN)
X(timing_del_Setup_SN_RN)
X(timing_del_TOBF_ctrl)
X(timing_del_bot_SB_couty2)
X(timing_del_bot_SB_pouty2)
X(timing_del_bot_couty2)
X(timing_del_bot_glb_couty2)
X(timing_del_bot_glb_pouty2)
X(timing_del_bot_pouty2)
X(timing_del_ddel_LVDS_r_OBFummy)
X(timing_del_dummy)
X(timing_del_left_SB_couty2)
X(timing_del_left_SB_pouty2)
X(timing_del_left_couty2)
X(timing_del_left_glb_couty2)
X(timing_del_left_glb_pouty2)
X(timing_del_left_pouty2)
X(timing_del_min_route_SB)
X(timing_del_r_OBF)
X(timing_del_sb_drv)
X(timing_del_special_RAM_I)
X(timing_del_violation_common)
X(timing_glbout_CLK0_0_CLK_FB0)
X(timing_glbout_CLK0_0_CLK_FB1)
X(timing_glbout_CLK0_0_CLK_FB2)
X(timing_glbout_CLK0_0_CLK_FB3)
X(timing_glbout_CLK0_0_GLB0)
X(timing_glbout_CLK0_1_CLK_FB0)
X(timing_glbout_CLK0_1_CLK_FB1)
X(timing_glbout_CLK0_1_CLK_FB2)
X(timing_glbout_CLK0_1_CLK_FB3)
X(timing_glbout_CLK0_1_GLB0)
X(timing_glbout_CLK0_1_GLB1)
X(timing_glbout_CLK0_2_CLK_FB0)
X(timing_glbout_CLK0_2_CLK_FB1)
X(timing_glbout_CLK0_2_CLK_FB2)
X(timing_glbout_CLK0_2_CLK_FB3)
X(timing_glbout_CLK0_2_GLB0)
X(timing_glbout_CLK0_2_GLB2)
X(timing_glbout_CLK0_3_CLK_FB0)
X(timing_glbout_CLK0_3_CLK_FB1)
X(timing_glbout_CLK0_3_CLK_FB2)
X(timing_glbout_CLK0_3_CLK_FB3)
X(timing_glbout_CLK0_3_GLB0)
X(timing_glbout_CLK0_3_GLB3)
X(timing_glbout_CLK180_0_CLK_FB0)
X(timing_glbout_CLK180_0_CLK_FB1)
X(timing_glbout_CLK180_0_CLK_FB2)
X(timing_glbout_CLK180_0_CLK_FB3)
X(timing_glbout_CLK180_0_GLB0)
X(timing_glbout_CLK180_0_GLB2)
X(timing_glbout_CLK180_1_CLK_FB0)
X(timing_glbout_CLK180_1_CLK_FB1)
X(timing_glbout_CLK180_1_CLK_FB2)
X(timing_glbout_CLK180_1_CLK_FB3)
X(timing_glbout_CLK180_1_GLB1)
X(timing_glbout_CLK180_1_GLB2)
X(timing_glbout_CLK180_2_CLK_FB0)
X(timing_glbout_CLK180_2_CLK_FB1)
X(timing_glbout_CLK180_2_CLK_FB2)
X(timing_glbout_CLK180_2_CLK_FB3)
X(timing_glbout_CLK180_2_GLB2)
X(timing_glbout_CLK180_3_CLK_FB0)
X(timing_glbout_CLK180_3_CLK_FB1)
X(timing_glbout_CLK180_3_CLK_FB2)
X(timing_glbout_CLK180_3_CLK_FB3)
X(timing_glbout_CLK180_3_GLB2)
X(timing_glbout_CLK180_3_GLB3)
X(timing_glbout_CLK270_0_CLK_FB0)
X(timing_glbout_CLK270_0_CLK_FB1)
X(timing_glbout_CLK270_0_CLK_FB2)
X(timing_glbout_CLK270_0_CLK_FB3)
X(timing_glbout_CLK270_0_GLB0)
X(timing_glbout_CLK270_0_GLB3)
X(timing_glbout_CLK270_1_CLK_FB0)
X(timing_glbout_CLK270_1_CLK_FB1)
X(timing_glbout_CLK270_1_CLK_FB2)
X(timing_glbout_CLK270_1_CLK_FB3)
X(timing_glbout_CLK270_1_GLB1)
X(timing_glbout_CLK270_1_GLB3)
X(timing_glbout_CLK270_2_CLK_FB0)
X(timing_glbout_CLK270_2_CLK_FB1)
X(timing_glbout_CLK270_2_CLK_FB2)
X(timing_glbout_CLK270_2_CLK_FB3)
X(timing_glbout_CLK270_2_GLB2)
X(timing_glbout_CLK270_2_GLB3)
X(timing_glbout_CLK270_3_CLK_FB0)
X(timing_glbout_CLK270_3_CLK_FB1)
X(timing_glbout_CLK270_3_CLK_FB2)
X(timing_glbout_CLK270_3_CLK_FB3)
X(timing_glbout_CLK270_3_GLB3)
X(timing_glbout_CLK90_0_CLK_FB0)
X(timing_glbout_CLK90_0_CLK_FB1)
X(timing_glbout_CLK90_0_CLK_FB2)
X(timing_glbout_CLK90_0_CLK_FB3)
X(timing_glbout_CLK90_0_GLB0)
X(timing_glbout_CLK90_0_GLB1)
X(timing_glbout_CLK90_1_CLK_FB0)
X(timing_glbout_CLK90_1_CLK_FB1)
X(timing_glbout_CLK90_1_CLK_FB2)
X(timing_glbout_CLK90_1_CLK_FB3)
X(timing_glbout_CLK90_1_GLB1)
X(timing_glbout_CLK90_2_CLK_FB0)
X(timing_glbout_CLK90_2_CLK_FB1)
X(timing_glbout_CLK90_2_CLK_FB2)
X(timing_glbout_CLK90_2_CLK_FB3)
X(timing_glbout_CLK90_2_GLB1)
X(timing_glbout_CLK90_2_GLB2)
X(timing_glbout_CLK90_3_CLK_FB0)
X(timing_glbout_CLK90_3_CLK_FB1)
X(timing_glbout_CLK90_3_CLK_FB2)
X(timing_glbout_CLK90_3_CLK_FB3)
X(timing_glbout_CLK90_3_GLB1)
X(timing_glbout_CLK90_3_GLB3)
X(timing_glbout_CLK_REF_OUT0_CLK_FB0)
X(timing_glbout_CLK_REF_OUT0_CLK_FB1)
X(timing_glbout_CLK_REF_OUT0_CLK_FB2)
X(timing_glbout_CLK_REF_OUT0_CLK_FB3)
X(timing_glbout_CLK_REF_OUT0_GLB0)
X(timing_glbout_CLK_REF_OUT1_CLK_FB0)
X(timing_glbout_CLK_REF_OUT1_CLK_FB1)
X(timing_glbout_CLK_REF_OUT1_CLK_FB2)
X(timing_glbout_CLK_REF_OUT1_CLK_FB3)
X(timing_glbout_CLK_REF_OUT1_GLB1)
X(timing_glbout_CLK_REF_OUT2_CLK_FB0)
X(timing_glbout_CLK_REF_OUT2_CLK_FB1)
X(timing_glbout_CLK_REF_OUT2_CLK_FB2)
X(timing_glbout_CLK_REF_OUT2_CLK_FB3)
X(timing_glbout_CLK_REF_OUT2_GLB2)
X(timing_glbout_CLK_REF_OUT3_CLK_FB0)
X(timing_glbout_CLK_REF_OUT3_CLK_FB1)
X(timing_glbout_CLK_REF_OUT3_CLK_FB2)
X(timing_glbout_CLK_REF_OUT3_CLK_FB3)
X(timing_glbout_CLK_REF_OUT3_GLB3)
X(timing_glbout_FEEDBACK_delay)
X(timing_glbout_USR_FB0_CLK_FB0)
X(timing_glbout_USR_FB1_CLK_FB1)
X(timing_glbout_USR_FB2_CLK_FB2)
X(timing_glbout_USR_FB3_CLK_FB3)
X(timing_glbout_USR_GLB0_CLK_FB0)
X(timing_glbout_USR_GLB0_CLK_FB1)
X(timing_glbout_USR_GLB0_CLK_FB2)
X(timing_glbout_USR_GLB0_CLK_FB3)
X(timing_glbout_USR_GLB0_GLB0)
X(timing_glbout_USR_GLB1_CLK_FB0)
X(timing_glbout_USR_GLB1_CLK_FB1)
X(timing_glbout_USR_GLB1_CLK_FB2)
X(timing_glbout_USR_GLB1_CLK_FB3)
X(timing_glbout_USR_GLB1_GLB1)
X(timing_glbout_USR_GLB2_CLK_FB0)
X(timing_glbout_USR_GLB2_CLK_FB1)
X(timing_glbout_USR_GLB2_CLK_FB2)
X(timing_glbout_USR_GLB2_CLK_FB3)
X(timing_glbout_USR_GLB2_GLB2)
X(timing_glbout_USR_GLB3_CLK_FB0)
X(timing_glbout_USR_GLB3_CLK_FB1)
X(timing_glbout_USR_GLB3_CLK_FB2)
X(timing_glbout_USR_GLB3_CLK_FB3)
X(timing_glbout_USR_GLB3_GLB3)
X(timing_in_delayline_per_stage)
X(timing_io_sel_CLOCK0_GPIO_OUT)
X(timing_io_sel_CLOCK0_IN1)
X(timing_io_sel_CLOCK0_IN2)
X(timing_io_sel_CLOCK1_GPIO_OUT)
X(timing_io_sel_CLOCK1_IN1)
X(timing_io_sel_CLOCK1_IN2)
X(timing_io_sel_CLOCK2_GPIO_OUT)
X(timing_io_sel_CLOCK2_IN1)
X(timing_io_sel_CLOCK2_IN2)
X(timing_io_sel_CLOCK3_GPIO_OUT)
X(timing_io_sel_CLOCK3_IN1)
X(timing_io_sel_CLOCK3_IN2)
X(timing_io_sel_GPIO_IN_IN1)
X(timing_io_sel_GPIO_IN_IN2)
X(timing_io_sel_OUT1_GPIO_OUT)
X(timing_io_sel_OUT1_IN1)
X(timing_io_sel_OUT1_IN2)
X(timing_io_sel_OUT2_GPIO_EN)
X(timing_io_sel_OUT2_GPIO_OUT)
X(timing_io_sel_OUT3_GPIO_EN)
X(timing_io_sel_OUT3_GPIO_OUT)
X(timing_io_sel_OUT4_GPIO_EN)
X(timing_io_sel_OUT4_GPIO_OUT)
X(timing_io_sel_OUT4_IN1)
X(timing_io_sel_OUT4_IN2)
X(timing_mout_D2)
X(timing_mout_L2)
X(timing_mout_OUT1)
X(timing_mout_OUT2)
X(timing_out_delayline_per_stage)
X(timing_pll_clk_ref_i_clk_core0_o)
X(timing_pll_clk_ref_i_clk_core180_o)
X(timing_pll_clk_ref_i_clk_core270_o)
X(timing_pll_clk_ref_i_clk_core90_o)
X(timing_pll_clock_core0_i_clk_core0_o)
X(timing_pll_clock_core0_i_clk_core180_o)
X(timing_pll_clock_core0_i_clk_core270_o)
X(timing_pll_clock_core0_i_clk_core90_o)
X(timing_pll_locked_steady_reset_i_pll_locked_steady_o)