nextpnr/fpga_interchange/examples/tests/wire/run.tcl

yosys -import

read_verilog $::env(SOURCES)

synth_xilinx -nolutram -nowidelut -nosrl -nocarry -nodsp

# opt_expr -undriven makes sure all nets are driven, if only by the $undef
# net.
opt_expr -undriven
opt_clean

setundef -zero -params

write_json $::env(OUT_JSON)
Add examples invoking FPGA interchange nextpnr. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> 2021-02-16 21:24:15 +01:00			`yosys -import`

fpga_interchange: tests: add cmake functions Also move all tests in a tests directory Signed-off-by: Alessandro Comodi <acomodi@antmicro.com> 2021-03-12 13:53:09 +01:00			`read_verilog $::env(SOURCES)`
Add examples invoking FPGA interchange nextpnr. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> 2021-02-16 21:24:15 +01:00
			`synth_xilinx -nolutram -nowidelut -nosrl -nocarry -nodsp`

			`# opt_expr -undriven makes sure all nets are driven, if only by the $undef`
			`# net.`
			`opt_expr -undriven`
			`opt_clean`

			`setundef -zero -params`

fpga_interchange: tests: add cmake functions Also move all tests in a tests directory Signed-off-by: Alessandro Comodi <acomodi@antmicro.com> 2021-03-12 13:53:09 +01:00			`write_json $::env(OUT_JSON)`