some problems stemming from comparing a case-sensitive netlist
against a case-insensitive one. Verilog netlist reading does
not yet have support for macros other than "`include", and it
does not yet have support for bit vectors constructed with
braces ({}).
|
||
|---|---|---|
| .. | ||
| Depend | ||
| Makefile | ||
| console.tcl | ||
| netgen.sh.in | ||
| netgen.tcl.in | ||
| netgenexec.c | ||
| tclnetgen.c | ||
| tkcon.tcl | ||