Files
netgen/base
Tim Edwards d38bd77825 Additional fixes to the verilog parser, including handling the
inline-I/O syntax with "wire" (e.g., "input wire [3:0] test")
and addressed the failure to add buses declared in inline I/O
to the list of known buses.
2019-09-09 13:42:21 -04:00
..
2019-06-12 11:11:28 -04:00