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Tim Edwards
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instance is matched to a verilog module definition, and the SPICE instance is read before the verilog definition, forcing a placeholder cell to be created. Netgen will now make the assumption that the verilog ports are in the same order as the SPICE instance port order. At the same time, it will output a warning message that it is making this not-necessarily-warranted assumption. If the number of ports don't match or the placeholder did not come from a SPICE instance, then the placeholder pins are left alone.
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8 B
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2 lines
8 B
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1.5.281
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