Files
netgen/base
Tim Edwards 58d7e17231 Corrected basic problem with verilog instance pins not needing to
be in any specific order since all ports are named.  Also corrected
problem with pin names not using the same string matching function
as used for nets in general (which affects the ability to match
against different bus delimiters).
2018-04-16 15:41:20 -04:00
..