Files
netgen/base
Tim Edwards 44ec952872 Expanded the verilog parser to handle most forms of allowable wire and
assignment statements in verilog netlists, including assignment of
signal bundles.  Also corrected handling of signal bundles in pin
connections, which had been corrected in qflow's verilog parser but
not copied back to netgen.  Note that the syntax for signals multiplied
N times is still not handled.
2019-08-10 22:30:57 -04:00
..
2019-06-12 11:11:28 -04:00