Tim Edwards 09b2bb3316 Extended the verilog parser to account for the fact that there can ...

be whitespace between a wire/register name and its array delimiter.

2018-10-29 15:19:13 -04:00

..

console.tcl

Initial commit at Mon May 18 09:27:46 EDT 2015 by tim on stravinsky

2015-05-18 09:27:46 -04:00

Depend

Initial commit at Mon May 18 09:27:46 EDT 2015 by tim on stravinsky

2015-05-18 09:27:46 -04:00

Makefile

First pass at incorporating the efabless LVS manager GUI into the

2018-05-01 14:07:16 -04:00

netgen.sh.in

Changed the netgen shell script from "sh" to "bash" due to the

2018-08-08 11:28:04 -04:00

netgen.tcl.in

Fixed a script error that caused pins not to be reported in the

2018-04-26 08:00:47 -04:00

netgenexec.c

Initial commit at Mon May 18 09:27:46 EDT 2015 by tim on stravinsky

2015-05-18 09:27:46 -04:00

tclnetgen.c

Added new handling for verilog structural netlists, and fixed

2018-04-12 17:09:10 -04:00

tkcon.tcl

Initial commit at Mon May 18 09:27:46 EDT 2015 by tim on stravinsky

2015-05-18 09:27:46 -04:00

tmp.out

Extended the verilog parser to account for the fact that there can

2018-10-29 15:19:13 -04:00