Reverted a change from a long time ago regarding removal of zero

valued resistors connecting two ports.  I do not recall exactly
why I put that in but it appears to cause incorrect behavior.

VERSION

@@ -1 +1 @@
-1.5.311
+1.5.314

base/flatten.c

@@ -2019,7 +2019,7 @@ PrematchLists(char *name1, int file1, char *name2, int file2)
 					    }
 					}
 
-					/* Do NOT remove shorting devices that	*/
+					/* Beware remove shorting devices that	*/
 					/* connect two ports.  Otherwise the	*/
 					/* port lists get screwed up.  It is	*/
 					/* better in that case to force the	*/
@@ -2027,6 +2027,10 @@ PrematchLists(char *name1, int file1, char *name2, int file2)
 					/* This is ignored for a top-level cell	*/
 					/* because it will just show up as a	*/
 					/* port mismatch error as it should.	*/
+					/* (12/12/2025---disabling this worked;	*/
+					/* may need to go back to a failing	*/
+					/* example and determine how pin	*/
+					/* matching gets scrambled.)		*/
 
 					if ((not_top == TRUE) &&
 						(ecomp->cell1->class != CLASS_ISOURCE)) {
@@ -2039,7 +2043,13 @@ PrematchLists(char *name1, int file1, char *name2, int file2)
 						else if (ob2->node == node2)
 						    found2 = TRUE;
 						if (found1 && found2) {
-						    found = FALSE;
+						    Fprintf(stdout, "Warning: "
+							"zero-valued device connects "
+							"port %s to another port;  pin "
+							"matching may be affected.\n",
+							ob2->name);
+						    // found = FALSE;
+						    found = TRUE;
 						    break;
 						}
 					    }

base/netcmp.c

@@ -7544,6 +7544,11 @@ struct nlist *addproxies(struct hashlist *p, void *clientdata)
 	     }
 	     else {
 		lob = ob;
+		if (ob == NULL) {
+		    Fprintf(stdout, "Error:  Premature end of pin list on "
+			"instance %s.\n", firstpin->instance.name);
+		    break;
+		}
 		ob->type = i++;
 		ob = ob->next;
 	     }

base/verilog.c

@@ -76,7 +76,8 @@ struct hashdict verilogparams;
 // Global storage for verilog definitions
 struct hashdict verilogdefs;
 // Record file pointer that is associated with the hash tables
-int hashfile = -1;
+int hashfilep = -1;	/* for parameters */
+int hashfiled = -1;	/* for definitions */
 
 // Global storage for wire buses
 struct hashdict buses;
@@ -2999,18 +3000,25 @@ char *ReadVerilogTop(char *fname, int *fnum, int blackbox)
      hashfunc = hashcase;
   }
 
-  if ((hashfile != -1) && (hashfile != *fnum)) {
+  if ((hashfilep != -1) && (hashfilep != *fnum)) {
-      /* Started a new file, so remove all the parameters and definitions */
+      /* Started a new file, so remove all the parameters */
       RecurseHashTable(&verilogparams, freeprop);
       HashKill(&verilogparams);
+      hashfilep = -1;
+  }
+  if ((hashfiled != -1) && (hashfiled != *fnum)) {
+      /* Started a new file, so remove all the definitions */
       RecurseHashTable(&verilogdefs, freeprop);
       HashKill(&verilogdefs);
-      hashfile = -1;
+      hashfiled = -1;
   }
-  if (hashfile == -1) {
+  if (hashfilep == -1) {
       InitializeHashTable(&verilogparams, OBJHASHSIZE);
+      hashfilep = filenum;
+  }
+  if (hashfiled == -1) {
       InitializeHashTable(&verilogdefs, OBJHASHSIZE);
-      hashfile = *fnum;
+      hashfiled = filenum;
   }
   definitions = &verilogdefs;
 

tcltk/netgen.tcl.in

@@ -516,6 +516,14 @@ proc netgen::lvs { name1 name2 {setupfile setup.tcl} {logfile comp.out} args} {
 	    }
 	 }
 	 close $fsetup
+      	 if {$command != {}} {
+	    # Incomplete command.  Evaluate it to get a meaningful error message
+	    if {[catch {uplevel 1 [list namespace eval netgen $command]} msg]} {
+		set msg [string trimright $msg "\n"]
+		puts stderr "Error $setupfile:$sline (ignoring), $msg"
+		incr perrors
+	    }
+	 }
       } else {
 	 puts stdout "Error:  Cannot read the setup file $setupfile"
       }