Corrected an error in the code that handles no-connects as valid
pins for enabling parallel combinations, which could cause a crash. Added a "-force" option to "equate pins" to allow pins to be matched even on subcircuits that did not correctly match; this was done in conjuction with an extra option to the "lvs" command "-noflatten=" to pass a list of cellname to not be flattened even if they do not match. This is generally discouraged, as it prevents netgen from resolving differences between layout and schematic hierarchy, but it can be useful for checking that the hierarchy above a certain cell is correct, given that if a subcell is really unmatched, then its errors will keep propagating up the top level, making additional errors hard to diagnose.
This commit is contained in:
Tim Edwards
parent
20077d3d56
commit
fd72e24a86
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@ -5363,13 +5363,21 @@ PropertyMatch(struct objlist *ob1, int file1,
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/* WIP---Check for no-connect pins in merged devices on both sides. */
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/* Both sides should either have no-connects marked, or neither. */
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/* (Permutable pins may need to be handled correctly. . . */
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for (tp1 = ob1, tp2 = ob2; (tp1 != NULL) && tp1->type >= FIRSTPIN &&
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(tp2 != NULL) && tp2->type >= FIRSTPIN; tp1 = tp1->next, tp2 = tp2->next)
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{
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struct objlist *node1, *node2;
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node1 = Circuit1->nodename_cache[tp1->node];
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node2 = Circuit2->nodename_cache[tp2->node];
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if (file1 == Circuit1->file)
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node1 = Circuit1->nodename_cache[tp1->node];
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else
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node1 = Circuit2->nodename_cache[tp1->node];
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if (file2 == Circuit1->file)
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node2 = Circuit1->nodename_cache[tp2->node];
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else
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node2 = Circuit2->nodename_cache[tp2->node];
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if (node1->instance.flags != node2->instance.flags)
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{
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@ -352,7 +352,7 @@ proc netgen::convert_to_json {filename lvs_final} {
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close $fjson
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}
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#----------------------------------------------------------------
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#-----------------------------------------------------------------------
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# Define the "lvs" command as a way of calling the netgen options
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# for standard compare, essentially the same as the old "netcomp"
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# standalone program.
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@ -361,14 +361,20 @@ proc netgen::convert_to_json {filename lvs_final} {
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# although if the cells have not been read in yet, then the
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# original syntax of filename or {filename cellname} is required.
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#
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# "args" is passed to verify and may therefore contain only the
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# value "-list" or nothing. If "-list", then output is returned
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# as a nested list.
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#----------------------------------------------------------------
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# "args" may be "-list", "-json", or "-blackbox".
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# "-list" returns output as a nested list.
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# "-json" creates a .json-format output file in addition to stdout.
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# "-blackbox" treats empty cells as black-box entries.
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# "-noflatten={list}" is a list of cells not to flatten if mismatched.
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# i.e., the cells are expected to match and any mismatch cannot be
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# expected to be resolved by flattening the contents of the mismatched
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# cells.
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#-----------------------------------------------------------------------
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proc netgen::lvs { name1 name2 {setupfile setup.tcl} {logfile comp.out} args} {
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set dolist 0
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set dojson 0
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set noflat {}
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foreach arg $args {
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if {$arg == "-list"} {
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puts stdout "Generating list result"
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@ -382,6 +388,9 @@ proc netgen::lvs { name1 name2 {setupfile setup.tcl} {logfile comp.out} args} {
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} elseif {$arg == "-blackbox"} {
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puts stdout "Treating empty subcircuits as black-box cells"
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netgen::model blackbox on
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} elseif {[string first "-noflatten=" $arg] == 0} {
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set noflat [string trim [string range $arg 11 end] \"\{\}]
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puts stdout "Will not flatten these subcells: $noflat"
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}
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}
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@ -501,6 +510,7 @@ proc netgen::lvs { name1 name2 {setupfile setup.tcl} {logfile comp.out} args} {
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return
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}
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set properr {}
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set matcherr {}
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set pinsgood 0
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while {$endval != {}} {
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if {$dolist == 1} {
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@ -529,9 +539,30 @@ proc netgen::lvs { name1 name2 {setupfile setup.tcl} {logfile comp.out} args} {
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# Flatten the non-matching subcircuit (but not the top-level cells)
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if {[netgen::print queue] != {}} {
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netgen::log put " Flattening non-matched subcircuits $endval"
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netgen::flatten class "[lindex $endval 0] $fnum1"
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netgen::flatten class "[lindex $endval 1] $fnum2"
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if {([lsearch $noflat [lindex $endval 0]] == -1) &&
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([lsearch $noflat [lindex $endval 1]] == -1)} {
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netgen::log put " Flattening non-matched subcircuits $endval"
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netgen::flatten class "[lindex $endval 0] $fnum1"
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netgen::flatten class "[lindex $endval 1] $fnum2"
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} else {
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netgen::log put " Continuing with black-boxed subcircuits $endval"
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lappend matcherr [lindex $endval 0]
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# Match pins
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netgen::log echo off
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if {$dolist == 1} {
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set result [equate -list -force pins "$fnum1 [lindex $endval 0]" \
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"$fnum2 [lindex $endval 1]"]
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} else {
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set result [equate -force pins "$fnum1 [lindex $endval 0]" \
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"$fnum2 [lindex $endval 1]"]
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}
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if {$result != 0} {
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equate classes "$fnum1 [lindex $endval 0]" \
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"$fnum2 [lindex $endval 1]"
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}
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set pinsgood $result
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netgen::log echo on
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}
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}
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} else {
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# Match pins
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@ -554,9 +585,32 @@ proc netgen::lvs { name1 name2 {setupfile setup.tcl} {logfile comp.out} args} {
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} else {
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# Flatten the non-matching subcircuit (but not the top-level cells)
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if {[netgen::print queue] != {}} {
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netgen::log put " Flattening non-matched subcircuits $endval"
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netgen::flatten class "[lindex $endval 0] $fnum1"
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netgen::flatten class "[lindex $endval 1] $fnum2"
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if {([lsearch $noflat [lindex $endval 1]] == -1) &&
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([lsearch $noflat [lindex $endval 1]] == -1)} {
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netgen::log put " Flattening non-matched subcircuits $endval"
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netgen::flatten class "[lindex $endval 0] $fnum1"
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netgen::flatten class "[lindex $endval 1] $fnum2"
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} else {
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netgen::log put " Continuing with black-boxed subcircuits $endval"
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lappend matcherr [lindex $endval 0]
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netgen::log put " Continuing with black-boxed subcircuits $endval"
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lappend matcherr [lindex $endval 0]
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# Match pins
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netgen::log echo off
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if {$dolist == 1} {
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set result [equate -list -force pins "$fnum1 [lindex $endval 0]" \
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"$fnum2 [lindex $endval 1]"]
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} else {
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set result [equate -force pins "$fnum1 [lindex $endval 0]" \
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"$fnum2 [lindex $endval 1]"]
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}
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if {$result != 0} {
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equate classes "$fnum1 [lindex $endval 0]" \
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"$fnum2 [lindex $endval 1]"
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}
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set pinsgood $result
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netgen::log echo on
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}
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}
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}
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netgen::log echo off
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@ -579,6 +633,9 @@ proc netgen::lvs { name1 name2 {setupfile setup.tcl} {logfile comp.out} args} {
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if {$properr != {}} {
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netgen::log put "The following cells had property errors: $properr\n"
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}
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if {$matcherr != {}} {
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netgen::log put "The following subcells failed to match: $matcherr\n"
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}
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if {$dolog} {
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netgen::log end
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}
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@ -2827,11 +2827,13 @@ _netcmp_equate(ClientData clientData,
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char *name1 = NULL, *name2 = NULL, *optstart;
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struct nlist *tp1, *tp2, *SaveC1, *SaveC2;
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struct objlist *ob1, *ob2;
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struct ElementClass *saveEclass = NULL;
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struct NodeClass *saveNclass = NULL;
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int file1, file2;
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int i, l1, l2, ltest, lent, dolist = 0;
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int i, l1, l2, ltest, lent, dolist = 0, doforce = 0;
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Tcl_Obj *tobj1, *tobj2, *tobj3;
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if (objc > 1) {
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while (objc > 1) {
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optstart = Tcl_GetString(objv[1]);
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if (*optstart == '-') optstart++;
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if (!strcmp(optstart, "list")) {
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@ -2839,6 +2841,13 @@ _netcmp_equate(ClientData clientData,
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objv++;
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objc--;
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}
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else if (!strcmp(optstart, "force")) {
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doforce = 1;
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objv++;
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objc--;
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}
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else
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break;
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}
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if ((objc != 2) && (objc != 4) && (objc != 6)) {
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@ -2996,6 +3005,12 @@ _netcmp_equate(ClientData clientData,
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break;
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case PINS_IDX:
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if ((ElementClasses != NULL) && (doforce == TRUE)) {
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saveEclass = ElementClasses;
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saveNclass = NodeClasses;
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ElementClasses = NULL;
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NodeClasses = NULL;
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}
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if ((ElementClasses == NULL) && (auto_blackbox == FALSE)) {
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if (CurrentCell == NULL) {
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Fprintf(stderr, "Equate elements: no current cell.\n");
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@ -3058,6 +3073,12 @@ _netcmp_equate(ClientData clientData,
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/* Recover temporarily set global variables (see above) */
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Circuit1 = SaveC1;
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Circuit2 = SaveC2;
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/* Recover ElementClasses if forcing pins on mismatched circuits */
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if (doforce == TRUE) {
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ElementClasses = saveEclass;
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NodeClasses = saveNclass;
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}
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}
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break;
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