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netgen
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Merge branch 'master' into netgen-1.5

This commit is contained in:
Tim Edwards 2020-03-06 03:00:39 -05:00
parent 0490959b07 983c654086
commit fc4e659725
5 changed files with 21 additions and 8 deletions
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2
VERSION
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@ -1 +1 @@
1.5.142 1.5.143

3
base/netcmp.c
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@ -4436,12 +4436,13 @@ int PropertyOptimize(struct objlist *ob, struct nlist *tp, int run, int series,
if (vl == NULL) { if (vl == NULL) {
if (kl->type != vlist[p][j]->type) if (kl->type != vlist[p][j]->type)
PromoteProperty(kl, vl2); PromoteProperty(kl, vl2);
vl = &dfltvl;
} }
else { else {
if (kl->type != vlist[p][i]->type) if (kl->type != vlist[p][i]->type)
PromoteProperty(kl, vl); PromoteProperty(kl, vl);
vl2 = &dfltvl;
} }
vl = &dfltvl;
dfltvl.type = kl->type; dfltvl.type = kl->type;
switch (kl->type) { switch (kl->type) {
case PROP_STRING: case PROP_STRING:

12
base/spice.c
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@ -1983,11 +1983,15 @@ void IncludeSpice(char *fname, int parent, struct cellstack **CellStackPtr,
if (strchr(fname, '.') == NULL) { if (strchr(fname, '.') == NULL) {
SetExtension(name, fname, SPICE_EXTENSION); SetExtension(name, fname, SPICE_EXTENSION);
filenum = OpenParseFile(name, parent); filenum = OpenParseFile(name, parent);
} if (filenum < 0) {
if (filenum < 0) { Fprintf(stderr, "Error in SPICE file include: No file %s\n", name);
Fprintf(stderr,"Error in SPICE file include: No file %s\n",name); return;
return; }
} }
else {
Fprintf(stderr, "Error in SPICE file include: No file %s\n", fname);
return;
}
} }
} }
ReadSpiceFile(fname, parent, CellStackPtr, blackbox); ReadSpiceFile(fname, parent, CellStackPtr, blackbox);

8
base/verilog.c
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@ -2043,11 +2043,15 @@ void IncludeVerilog(char *fname, int parent, struct cellstack **CellStackPtr,
if (strchr(fname, '.') == NULL) { if (strchr(fname, '.') == NULL) {
SetExtension(name, fname, VERILOG_EXTENSION); SetExtension(name, fname, VERILOG_EXTENSION);
filenum = OpenParseFile(name, parent); filenum = OpenParseFile(name, parent);
if (filenum < 0) {
fprintf(stderr,"Error in Verilog file include: No file %s\n", name);
return;
}
} }
if (filenum < 0) { else {
fprintf(stderr,"Error in Verilog file include: No file %s\n", fname); fprintf(stderr,"Error in Verilog file include: No file %s\n", fname);
return; return;
} }
} }
} }
ReadVerilogFile(fname, parent, CellStackPtr, blackbox); ReadVerilogFile(fname, parent, CellStackPtr, blackbox);

4
tcltk/tclnetgen.c
View File

@ -2974,6 +2974,10 @@ _netcmp_equate(ClientData clientData,
Fprintf(stdout, "Warning: Equate pins: cell %s " Fprintf(stdout, "Warning: Equate pins: cell %s "
"has no definition, treated as a black box.\n", name2); "has no definition, treated as a black box.\n", name2);
} }
// If a cell in either circuit is marked as a black box, then
// the cells in both circuits should be marked as a black box.
tp1->flags |= CELL_PLACEHOLDER;
tp2->flags |= CELL_PLACEHOLDER;
} }
else { else {
Fprintf(stdout, "Equate pins: cell %s and/or %s " Fprintf(stdout, "Equate pins: cell %s and/or %s "