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netgen
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Merge branch 'master' into netgen-1.5

This commit is contained in:
Tim Edwards 2021-10-24 03:00:12 -04:00
parent 97058c5017 4c4bad08f2
commit 610eebb758
3 changed files with 10 additions and 46 deletions
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2
VERSION
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@ -1 +1 @@
1.5.205 1.5.206

38
base/flatten.c
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@ -264,9 +264,6 @@ int flattenInstancesOf(char *name, int fnum, char *instance)
int notdone, rnodenum; int notdone, rnodenum;
char tmpstr[1024]; char tmpstr[1024];
int nextnode, oldmax, numflat = 0; int nextnode, oldmax, numflat = 0;
struct objlist *myObject_p, *myPort_p;
struct objlist *myFirstPin_p, *myPin_p;
int myDeleteCount = 0;
#if !OLDPREFIX #if !OLDPREFIX
int prefixlength; int prefixlength;
#endif #endif
@ -602,38 +599,6 @@ int flattenInstancesOf(char *name, int fnum, char *instance)
} }
CacheNodeNames(ThisCell); CacheNodeNames(ThisCell);
ThisCell->dumped = 1; /* indicate cell has been flattened */ ThisCell->dumped = 1; /* indicate cell has been flattened */
// Remove disconnected ports.
// Fprintf(stdout, "DEBUG: check pins for %s of %d\n", name, fnum);
myFirstPin_p = NULL;
// Save first pin definition so we don't have to search for each port
for (myObject_p = ThisCell->cell; myObject_p != NULL; myObject_p = myObject_p->next) {
if (myObject_p->type >= FIRSTPIN) {
myFirstPin_p = myObject_p;
break;
}
}
if (myFirstPin_p != NULL) { // Not a black box. Black boxes contain no pins.
// For each port, check for pin connection. If none, mark for deletion.
// Assumes that all ports occur at the beginning of the list
for (myPort_p = ThisCell->cell; myPort_p != NULL && IsPort(myPort_p);
myPort_p = myPort_p->next ) {
for (myPin_p = myFirstPin_p; myPin_p != NULL; myPin_p = myPin_p->next) {
if (myPort_p->node == myPin_p->node) { // only need to find one connection
break;
}
}
if (myPin_p == NULL) { // mark disconnected ports
myDeleteCount++;
myPort_p->node = -2;
}
}
if (myDeleteCount > 0) { // delete disconnected ports
CleanupPins(name, fnum);
}
}
return numflat; return numflat;
} }
@ -1617,8 +1582,7 @@ PrematchLists(char *name1, int file1, char *name2, int file2)
} }
} }
else { else {
// Apply recursive flattening when a cell exists in match = 0;
// one circuit but not the other.
break; break;
} }
} }

6
tcltk/netgen.tcl.in
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@ -567,8 +567,7 @@ proc netgen::lvs { name1 name2 {setupfile setup.tcl} {logfile comp.out} args} {
netgen::flatten class "[lindex $endval 1] $fnum2" netgen::flatten class "[lindex $endval 1] $fnum2"
} else { } else {
netgen::log put " Continuing with black-boxed subcircuits $endval\n" netgen::log put " Continuing with black-boxed subcircuits $endval\n"
lappend matcherr [lindex $endval 0]"(1)" lappend matcherr [lindex $endval 0]
lappend matcherr [lindex $endval 1]"(2)"
# Match pins # Match pins
netgen::log echo off netgen::log echo off
if {$dolist == 1} { if {$dolist == 1} {
@ -618,7 +617,8 @@ proc netgen::lvs { name1 name2 {setupfile setup.tcl} {logfile comp.out} args} {
} else { } else {
netgen::log put " Continuing with black-boxed subcircuits $endval\n" netgen::log put " Continuing with black-boxed subcircuits $endval\n"
lappend matcherr [lindex $endval 0]"(1)" lappend matcherr [lindex $endval 0]"(1)"
lappend matcherr [lindex $endval 1]"(2)" netgen::log put " Continuing with black-boxed subcircuits $endval\n"
lappend matcherr [lindex $endval 0]"(2)"
# Match pins # Match pins
netgen::log echo off netgen::log echo off
if {$dolist == 1} { if {$dolist == 1} {