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Extended the verilog parser to account for the fact that there can

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be whitespace between a wire/register name and its array delimiter.
This commit is contained in:
Tim Edwards
2018-10-29 15:19:13 -04:00
parent 41665036e9
commit 09b2bb3316
2 changed files with 4418 additions and 0 deletions
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base/verilog.c
+13
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@@ -1208,6 +1208,19 @@ skip_endmodule:
new_port->net = strsave(nexttok);
/* Read array information along with name; will be parsed later */
SkipTokComments(VLOG_DELIMITERS);
if (match(nexttok, "[")) {
/* Check for space between name and array identifier */
SkipTokComments(VLOG_PIN_NAME_DELIMITERS);
if (!match(nexttok, ")")) {
char *expnet;
expnet = (char *)MALLOC(strlen(new_port->net)
+ strlen(nexttok) + 2);
sprintf(expnet, "%s[%s", new_port->net, nexttok);
FREE(new_port->net);
new_port->net = expnet;
}
SkipTokComments(VLOG_DELIMITERS);
}
if (!match(nexttok, ")")) {
Printf("Badly formed subcircuit pin line at \"%s\"\n", nexttok);
SkipNewLine(VLOG_DELIMITERS);