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Corrected a rather obscure error in which an otherwise unconnected port-to-port short (formed by "assign" in verilog or zero-valued resistors in SPICE) does not get checked when counting nodes before adding a proxy pin to a subcircuit in that cell, causing the proxy pin to be assigned the same node number and forming an unintended connection to the port-to-port connecting net.
2024-10-01 04:11:53 +02:00
1.5.279