mirror of
https://github.com/RTimothyEdwards/magic.git
synced 2026-09-02 11:08:30 +02:00
Tim Edwards
c001de3d9d
reading GDS files, caused by an unneeded change to pass both the "original" filename and the actual filename when handling compressed files---The original filename is unneeded. (2) Implemented several new methods for parasitic extraction. The first is an option offset value to apply to sidewall calculations. This handles issues where actual wire separation is different from drawn wire separation, which can be significant for the 1/d calculation of sidewall coupling. The second method is to use the recently-added fringe halo to compute the coupling of the fringe capacitance to nearby wires. Prior to this change, all fringe capacitance was applied to surfaces directly under a wire edge as if the fringe capacitance did not extend outward from the edge. Now the capacitance is properly pro-rated for the position of any overlapped shape inside the fringing field. Finally, the third method added is a new search algorithm for finding the nearest shapes along the length of a boundary. This is used for sidewall coupling and fringe shielding, where the nearest shape dominates the coupling, and any shapes behind are shielded and may (to first order) be ignored. Previously, the entire halo was searched without regard to shapes shielding other shapes behind, and a recent correction added an ad-hoc search for blocking shapes that was inefficient and not always correct. The new method is both efficient and accurate.
112 lines
3.9 KiB
C
112 lines
3.9 KiB
C
/*
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* extract.h --
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*
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* Defines the exported interface to the circuit extractor.
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*
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* rcsid "$Header: /usr/cvsroot/magic-8.0/extract/extract.h,v 1.3 2009/01/30 03:51:02 tim Exp $"
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*
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* *********************************************************************
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* * Copyright (C) 1985, 1990 Regents of the University of California. *
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* * Permission to use, copy, modify, and distribute this *
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* * software and its documentation for any purpose and without *
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* * fee is hereby granted, provided that the above copyright *
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* * notice appear in all copies. The University of California *
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* * makes no representations about the suitability of this *
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* * software for any purpose. It is provided "as is" without *
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* * express or implied warranty. Export of this software outside *
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* * of the United States of America may require an export license. *
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* *********************************************************************
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*
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*/
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#ifndef _EXTRACT_H
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#define _EXTRACT_H
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#include "utils/magic.h"
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/* Extractor warnings */
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#define EXTWARN_DUP 0x01 /* Warn if two nodes have the same name */
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#define EXTWARN_LABELS 0x02 /* Warn if connecting to unlabelled subcell
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* node.
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*/
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#define EXTWARN_FETS 0x04 /* Warn about badly constructed fets */
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#define EXTWARN_ALL (EXTWARN_DUP|EXTWARN_LABELS|EXTWARN_FETS)
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extern int ExtDoWarn; /* Bitmask of above */
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/* Known devices (see ExtTech.c and ExtBasic.c) */
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/* Make sure these match extDevTable in extract/ExtBasic.c and */
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/* also extflat/EFread.c */
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#define DEV_FET 0 /* FET w/area, perimeter declared */
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#define DEV_MOSFET 1 /* FET w/length, width declared */
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#define DEV_ASYMMETRIC 2 /* Like MOSFET but D,S not swappable */
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#define DEV_BJT 3 /* Bipolar Junction Transistor */
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#define DEV_RES 4 /* Resistor */
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#define DEV_CAP 5 /* Capacitor */
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#define DEV_CAPREV 6 /* Capacitor, terminals reversed */
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#define DEV_VOLT 7 /* Voltage source (used for shorts) */
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#define DEV_DIODE 8 /* Diode */
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#define DEV_PDIODE 9 /* pDiode, same as Diode */
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#define DEV_NDIODE 10 /* nDiode, terminals reversed */
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#define DEV_SUBCKT 11 /* general-purpose subcircuit */
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#define DEV_RSUBCKT 12 /* Resistor-like subcircuit. */
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#define DEV_MSUBCKT 13 /* MOSFET-like subcircuit. */
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#define DEV_CSUBCKT 14 /* Capacitor-like subcircuit. */
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/* Device names for .ext file output (new in version 7.2) */
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/* (defined in extract/ExtBasic.c *and* extflat/EFread.c) */
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extern char *extDevTable[];
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/* Extractor options */
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#define EXT_DOADJUST 0x001 /* Extract hierarchical adjustments */
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#define EXT_DOCAPACITANCE 0x002 /* Extract capacitance */
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#define EXT_DOCOUPLING 0x004 /* Extract coupling capacitance */
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#define EXT_DORESISTANCE 0x008 /* Extract resistance */
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#define EXT_DOLENGTH 0x010 /* Extract pathlengths */
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#define EXT_DOFRINGEHALO 0x020 /* Distributed fringe capacitance */
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#define EXT_DOALL 0x03f /* ALL OF THE ABOVE */
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#define EXT_DOLOCAL 0x040 /* Write to local directory only */
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#define EXT_DOLABELCHECK 0x080 /* Check for connections by label */
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#define EXT_DOALIASES 0x100 /* Output all node aliases */
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extern int ExtOptions; /* Bitmask of above */
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/* Options for "extract unique" */
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#define EXT_UNIQ_ALL 0
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#define EXT_UNIQ_TAGGED 1
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#define EXT_UNIQ_NOPORTS 2
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#define EXT_UNIQ_NOTOPPORTS 3
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extern bool ExtTechLine();
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extern void ExtTechInit();
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extern void ExtTechFinal();
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extern void ExtSetStyle();
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extern void ExtPrintStyle();
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extern void ExtRevertSubstrate();
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extern Plane *ExtCell();
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extern void ExtractOneCell();
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extern int ExtGetGateTypesMask();
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extern int ExtGetDiffTypesMask();
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#ifdef MAGIC_WRAPPER
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extern bool ExtGetDevInfo();
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extern bool ExtCompareStyle();
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#endif
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#ifdef THREE_D
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extern void ExtGetZAxis();
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#endif
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extern void ExtDumpCaps();
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extern int extEnumTilePerim();
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extern Plane *extPrepSubstrate();
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#endif /* _EXTRACT_H */
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