mirror of
https://github.com/RTimothyEdwards/magic.git
synced 2026-08-31 18:25:50 +02:00
Patrick Kurth
ea03883829
Added a ARG_UNUSED macro in utils/magic.h, which produces a simple cast to void to silence the warnings. The reasons this is used as opposed to an attribute is that most compilers should support this. Besides this, the macro can be easily searched for in the future to potentially remove (where possible) the unused parameters.
833 lines
20 KiB
C
833 lines
20 KiB
C
/*
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* SimExtract.c
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*
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* This file provides routines to extract a single node name from the
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* Magic circuit. Some of this code is based on the Magic extract
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* module.
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*
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* *********************************************************************
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* * Copyright (C) 1985, 1990 Regents of the University of California. *
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* * Permission to use, copy, modify, and distribute this *
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* * software and its documentation for any purpose and without *
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* * fee is hereby granted, provided that the above copyright *
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* * notice appear in all copies. The University of California *
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* * makes no representations about the suitability of this *
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* * software for any purpose. It is provided "as is" without *
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* * express or implied warranty. Export of this software outside *
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* * of the United States of America may require an export license. *
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* *********************************************************************
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* of California.
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*/
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#include <stdio.h>
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#include <string.h>
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#include <math.h>
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#include "tcltk/tclmagic.h"
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#include "utils/magic.h"
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#include "utils/geometry.h"
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#include "utils/geofast.h"
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#include "tiles/tile.h"
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#include "utils/hash.h"
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#include "database/database.h"
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#include "utils/malloc.h"
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#include "textio/textio.h"
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#include "debug/debug.h"
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#include "extract/extract.h"
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#include "extract/extractInt.h"
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#include "utils/signals.h"
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#include "windows/windows.h"
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#include "dbwind/dbwind.h"
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#include "utils/styles.h"
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#include "utils/stack.h"
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#include "sim/sim.h"
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/* C99 compat */
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#include "extract/extract.h"
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/* When performing node name extraction, we mark all tiles of a node
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* as we walk through the database. Since nodes can span multiple cells,
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* we need to keep a list off all cell definitions which we marked during
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* the search so we can erase these marks when we are finished.
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*/
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typedef struct def_list_elt
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{
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CellDef *dl_def;
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struct def_list_elt *dl_next;
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} DefListElt;
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/* When the node name is extracted, all the labels associated with the
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* name are contained in a NodeRegion data structure. We save all the
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* node regions created during the name search, freeing them when we are
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* finished.
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*/
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static DefListElt *DefList = (DefListElt *) NULL;
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/* list of cell defs used in the node name search */
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static NodeRegion *NodeRegList = (NodeRegion *) NULL;
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/* list of the nodes found in the current selection */
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extern Stack *extNodeStack;
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/* stack used to process node tiles */
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static ExtStyle *simExtStyle = NULL;
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/*
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* Mask with a bit set for every type of transistor.
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*/
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TileTypeBitMask SimTransMask;
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/*
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* Mask indicating which tile types may form a transistor
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* terminal (source/drain).
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*/
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TileTypeBitMask SimSDMask;
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/*
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* A mask indicating which tile types may be the active part
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* of a transistor. if type 't' is a possible transistor terminal,
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* then SimFetMask[t] indicates which tile types to search for the
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* 'gate' part.
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*/
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TileTypeBitMask SimFetMask[TT_MAXTYPES];
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/*
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* Mask of planes for which SimFetMask is non-zero.
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*/
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PlaneMask SimFetPlanes;
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/*
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*----------------------------------------------------------------
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* SimAddDefList --
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*
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* This procedure adds a cell definition to the DefList. A cell
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* definition is added only if is not already in the list.
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*
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* Results:
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* None.
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*
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* Side effects:
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* The cell may be added to the list.
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*
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*----------------------------------------------------------------
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*/
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void
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SimAddDefList(
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CellDef *newdef)
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{
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DefListElt *d;
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/* check to see if the cell def is already in our list */
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for (d = DefList; d != (DefListElt *) NULL; d = d->dl_next) {
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if (d->dl_def == newdef) {
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return;
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}
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}
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/* add the cell def to the list */
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if (DefList == (DefListElt *) NULL) {
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DefList = (DefListElt *) mallocMagic((unsigned) (sizeof(DefListElt)));
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DefList->dl_def = newdef;
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DefList->dl_next = (DefListElt *) NULL;
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return;
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}
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else {
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d = (DefListElt *) mallocMagic((unsigned) (sizeof(DefListElt)));
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d->dl_next = DefList;
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d->dl_def = newdef;
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DefList= d;
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}
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}
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/*
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*----------------------------------------------------------------
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* SimInitDefList
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*
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* This procedure initializes the cell definition list. Any cell
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* definitions in the list have their tiles erased of the marks
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* we left during the node name search, and the space in the list
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* is freed.
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*
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* Results:
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* None.
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*
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* Side effects:
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* The cell definitions' tiles' marks we left are erased and the
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* list is set to NULL.
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*
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*----------------------------------------------------------------
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*/
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void
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SimInitDefList(void)
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{
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DefListElt *p, *q;
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p = q = DefList;
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while (p != (DefListElt *) NULL) {
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q = p;
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p = p->dl_next;
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ExtResetTiles(q->dl_def, extUnInit);
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freeMagic(q);
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}
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DefList = (DefListElt *) NULL;
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}
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/*
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*----------------------------------------------------------------
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* SimAddNodeList
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*
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* This procedure prepends a node region to the node region list.
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*
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* Results:
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* None.
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*
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* Side effects:
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* The region next pointer is updated.
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*
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*----------------------------------------------------------------
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*/
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void
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SimAddNodeList(
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NodeRegion *newnode)
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{
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if( NodeRegList != (NodeRegion *) NULL )
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newnode->nreg_next = NodeRegList;
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NodeRegList = newnode;
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}
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/*
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*----------------------------------------------------------------
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* SimFreeNodeRegs
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*
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* This procedure frees the label regions stored in the list.
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*
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* Results:
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* None.
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*
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* Side effects:
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* The list is set to NULL.
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*
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*----------------------------------------------------------------
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*/
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void
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SimFreeNodeRegs(void)
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{
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if( NodeRegList != (NodeRegion *) NULL ) /* sanity */
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ExtFreeLabRegions((LabRegion *) NodeRegList );
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NodeRegList = (NodeRegion *) NULL;
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}
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/*
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*----------------------------------------------------------------
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* SimInitConnTables --
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*
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* Initialize the connectivity tables for finding transistors connected
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* to the region being searched.
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*----------------------------------------------------------------
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*/
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int
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SimInitConnTables(void)
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{
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int i, t, sd;
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ExtDevice *devptr;
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SimTransMask = ExtCurStyle->exts_deviceMask;
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TTMaskZero( &SimSDMask );
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for( t = TT_TECHDEPBASE; t < DBNumTypes; t++ )
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{
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devptr = ExtCurStyle->exts_device[t];
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for (i = 0; !TTMaskHasType(&devptr->exts_deviceSDTypes[i],
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TT_SPACE); i++)
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{
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TTMaskSetMask( &SimSDMask, &devptr->exts_deviceSDTypes[i] );
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TTMaskZero( &SimFetMask[t] );
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}
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}
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SimFetPlanes = 0;
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for (t = TT_TECHDEPBASE; t < DBNumTypes; t++)
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{
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if (TTMaskHasType(&SimTransMask, t))
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{
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devptr = ExtCurStyle->exts_device[t];
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for (sd = TT_TECHDEPBASE; sd < DBNumTypes; sd++)
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{
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for (i = 0; !TTMaskHasType(&devptr->exts_deviceSDTypes[i],
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TT_SPACE); i++)
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{
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if (TTMaskHasType(&devptr->exts_deviceSDTypes[i], sd))
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{
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TTMaskSetType(&SimFetMask[sd], t);
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SimFetPlanes |= PlaneNumToMaskBit(DBPlane(t));
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}
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}
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}
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}
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}
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simExtStyle = ExtCurStyle;
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return 0;
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}
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#define IsTransGate( T ) ( TTMaskHasType( &SimTransMask, T ) )
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#define IsTransTerm( T ) ( TTMaskHasType( &SimSDMask, T ) )
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typedef struct
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{
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NodeRegion *region; /* Node to which this terminal is connected */
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int pnum; /* Lowest numbered plane in this region */
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Point pos; /* Lower-leftmost point for this node */
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} TransTerm;
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typedef struct
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{
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LabRegion *t_dummy; /* UNUSED */
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int t_pnum; /* Lowest numbered plane in this region */
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int t_type; /* Type of tile that contains lreg_ll */
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Point t_ll; /* Lower-leftmost point of 'gate' region */
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int t_nterm; /* number of terminals (at most 2) */
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bool t_do_terms; /* Set if we should collect terminals */
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TransTerm t_term[10]; /* transistor 'source/drain' terminal(s) */
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} SimTrans;
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static Tile *gateTile; /* Set to point to a transistor tile
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* whose gate is connected to the
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* node being searched
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*/
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static Tile *sdTile; /* Set to point to a transistor tile
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* whose source/drain is connected
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* to the node being searched
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*/
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static SimTrans transistor; /* Transistor being extracted */
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typedef enum { ND_REGION, ND_NAME } RegOrName;
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typedef struct /* return value from SimFindOneNode */
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{
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RegOrName nd_what; /* ND_REGION, => region, ND_NAME => nd_name */
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NodeRegion *nd_region; /* The node region extracted */
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char *nd_name; /* The 'final' node name */
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} NodeSpec;
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/*
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*----------------------------------------------------------------
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* SimTxtorLabel --
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*
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* Return a string that identifies a node as a function of a transistor
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* position.
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*
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*----------------------------------------------------------------
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*/
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char *
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SimTxtorLabel(
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int nterm,
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const Transform *tm,
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SimTrans *trans)
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{
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static char name[30];
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Rect r1, r2;
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r1.r_ll = trans->t_ll;
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r1.r_xtop = r1.r_xbot + 1;
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r1.r_ytop = r1.r_ybot + 1;
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GeoTransRect( tm, &r1, &r2 );
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if( nterm > 1 )
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nterm = 1;
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sprintf( name, "@=%c%d,%d", "gsd"[nterm+1], r2.r_xbot, r2.r_ybot );
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return( name );
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}
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int
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SimSDTransFunc(
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Tile *tile,
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Tile **ptile)
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{
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*ptile = tile;
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return( 1 );
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}
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int
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SimTransTerms(
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Boundary *bp,
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SimTrans *trans)
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{
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TransTerm *term;
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Tile *tile = bp->b_outside;
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TileType type;
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NodeRegion *reg = (NodeRegion *) TiGetClientPTR(tile);
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int pNum;
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int i;
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if (IsSplit(tile)) {
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switch(bp->b_direction) {
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case BD_LEFT:
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type = TiGetRightType(tile);
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break;
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case BD_RIGHT:
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type = TiGetLeftType(tile);
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break;
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case BD_TOP:
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type = TiGetBottomType(tile);
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break;
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case BD_BOTTOM:
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type = TiGetTopType(tile);
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break;
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}
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}
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else
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type = TiGetTypeExact(tile);
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pNum = DBPlane(type);
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for( i = 0; i < trans->t_nterm; i++ )
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{
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term = &trans->t_term[i];
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if( term->region == reg )
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{
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if( pNum < term->pnum )
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{
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term->pnum = pNum;
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term->pos = tile->ti_ll;
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}
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else if( pNum == term->pnum )
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{
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if( LEFT(tile) < term->pos.p_x )
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term->pos = tile->ti_ll;
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else if( LEFT(tile) == term->pos.p_x &&
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BOTTOM(tile) < term->pos.p_y )
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term->pos.p_y = BOTTOM(tile);
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}
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return( 0 );
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}
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}
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term = &trans->t_term[ trans->t_nterm++ ];
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term->region = reg;
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term->pnum = pNum;
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term->pos = tile->ti_ll;
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return( 0 );
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}
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int
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SimTermNum(
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SimTrans *trans,
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NodeRegion *reg)
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{
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int i, changed;
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TransTerm *p1, *p2, tmp;
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do
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{
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changed = 0;
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for( i = 0; i < trans->t_nterm-1; i++ )
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{
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p1 = &(trans->t_term[i]);
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p2 = &(trans->t_term[i+1]);
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if( p2->pnum > p1->pnum )
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continue;
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else if( p2->pnum == p1->pnum )
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{
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if( p2->pos.p_x > p1->pos.p_x )
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continue;
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else if( p2->pos.p_x == p1->pos.p_x &&
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p2->pos.p_y > p1->pos.p_y )
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continue;
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}
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changed = 1;
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tmp = *p1;
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*p1 = *p2;
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*p2 = tmp;
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}
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}
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while( changed );
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for( i = 0; i < trans->t_nterm; i++ )
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{
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if( trans->t_term[i].region == reg )
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return( i );
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}
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/* should never get here */
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return( -1 );
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}
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int
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SimTransistorTile(
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Tile *tile,
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int pNum,
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FindRegion *arg)
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{
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ARG_UNUSED(arg);
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int i;
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TileType t;
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ExtDevice *devptr;
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extSetNodeNum((LabRegion *)&transistor, pNum, tile);
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if (transistor.t_do_terms)
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{
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t = TiGetType(tile);
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devptr = ExtCurStyle->exts_device[t];
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for (i = 0; !TTMaskHasType(&devptr->exts_deviceSDTypes[i],
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TT_SPACE); i++)
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extEnumTilePerim(tile, &devptr->exts_deviceSDTypes[i], pNum,
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SimTransTerms, (ClientData) &transistor );
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}
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return (0);
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}
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int
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SimFindTxtor(
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Tile *tile,
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int pNum,
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FindRegion *arg)
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{
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TileType type;
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extSetNodeNum( (LabRegion *) arg->fra_region, pNum, tile );
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if( ! SimUseCoords ) /* keep searching, forget transistors */
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return( 0 );
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type = TiGetType( tile );
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if( IsTransGate( type ) )
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{
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gateTile = tile; /* found a transistor gate, stop searching */
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return( 1 );
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}
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else if( IsTransTerm( type ) && sdTile == (Tile *) NULL )
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{
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Rect area;
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TITORECT( tile, &area );
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GEO_EXPAND( &area, 1, &area );
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for( pNum = PL_TECHDEPBASE; pNum < DBNumPlanes; pNum++ )
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if( PlaneMaskHasPlane( SimFetPlanes, pNum ) )
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{
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if( DBSrPaintArea((Tile *) NULL,
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arg->fra_def->cd_planes[pNum], &area, &SimFetMask[type],
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SimSDTransFunc, (ClientData) &sdTile ) )
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break;
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}
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}
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return( 0 );
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}
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/*
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*----------------------------------------------------------------
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* SimFindOneNode
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*
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* This procedure returns the node region for a tile which lies
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* in the node.
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*
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* Results:
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* A pointer to the node's node region data structure is returned.
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*
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* Side effects:
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* None.
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*
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*----------------------------------------------------------------
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*/
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NodeSpec *
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SimFindOneNode(
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SearchContext *sx,
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Tile *tile)
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{
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CellDef *def = sx->scx_use->cu_def;
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NodeRegion *reg;
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FindRegion arg;
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TileType type, loctype;
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static NodeSpec ret;
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/* Allocate a new node */
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reg = (NodeRegion *) mallocMagic((unsigned) (sizeof(NodeRegion) ));
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reg->nreg_labels = (LabelList *) NULL;
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reg->nreg_cap = 0;
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reg->nreg_resist = 0;
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reg->nreg_pnum = DBNumPlanes;
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reg->nreg_next = (NodeRegion *) NULL;
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gateTile = sdTile = (Tile *) NULL;
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/* Find all connected paint in this cell */
|
|
arg.fra_connectsTo = ExtCurStyle->exts_nodeConn;
|
|
arg.fra_def = def;
|
|
|
|
if (IsSplit(tile))
|
|
type = SplitSide(tile) ? TiGetRightType(tile) : TiGetLeftType(tile);
|
|
else
|
|
type = TiGetTypeExact(tile);
|
|
|
|
arg.fra_pNum = DBPlane(type);
|
|
arg.fra_uninit = (ClientData) extUnInit;
|
|
arg.fra_region = (ExtRegion *) reg;
|
|
arg.fra_each = SimFindTxtor;
|
|
(void) ExtFindNeighbors( tile, arg.fra_pNum, &arg );
|
|
|
|
if( gateTile != (Tile *) NULL )
|
|
{
|
|
/* Determine the transistor position (leftmost-lowest tile) */
|
|
transistor.t_pnum = DBNumPlanes;
|
|
transistor.t_do_terms = FALSE;
|
|
|
|
TiSetClient(gateTile, extUnInit);
|
|
arg.fra_connectsTo = &SimTransMask;
|
|
|
|
if (IsSplit(tile))
|
|
loctype = SplitSide(gateTile) ? TiGetRightType(gateTile)
|
|
: TiGetLeftType(gateTile);
|
|
else
|
|
loctype = TiGetTypeExact(gateTile);
|
|
|
|
arg.fra_pNum = DBPlane(loctype);
|
|
arg.fra_uninit = (ClientData) extUnInit;
|
|
arg.fra_region = (ExtRegion *) reg;
|
|
arg.fra_each = SimTransistorTile;
|
|
(void) ExtFindNeighbors( gateTile, arg.fra_pNum, &arg );
|
|
|
|
/* Unmark current region since not all paint was traced */
|
|
arg.fra_connectsTo = ExtCurStyle->exts_nodeConn;
|
|
arg.fra_pNum = DBPlane(type);
|
|
arg.fra_uninit = (ClientData) reg;
|
|
arg.fra_region = (ExtRegion *) extUnInit;
|
|
arg.fra_each = (int (*)()) NULL;
|
|
(void) ExtFindNeighbors( tile, arg.fra_pNum, &arg );
|
|
|
|
freeMagic( reg );
|
|
|
|
ret.nd_name = SimTxtorLabel( -1, &sx->scx_trans, &transistor );
|
|
ret.nd_what = ND_NAME;
|
|
}
|
|
else if( sdTile != (Tile *) NULL )
|
|
{
|
|
int tNum;
|
|
|
|
SimAddNodeList( reg );
|
|
SimAddDefList( def );
|
|
|
|
transistor.t_pnum = DBNumPlanes;
|
|
transistor.t_nterm = 0;
|
|
transistor.t_do_terms = TRUE;
|
|
|
|
/* collect the transistor position, and its terminals */
|
|
arg.fra_connectsTo = &SimTransMask;
|
|
|
|
if (IsSplit(tile))
|
|
loctype = SplitSide(sdTile) ? TiGetRightType(sdTile)
|
|
: TiGetLeftType(sdTile);
|
|
else
|
|
loctype = TiGetTypeExact(sdTile);
|
|
|
|
arg.fra_pNum = DBPlane(loctype);
|
|
arg.fra_uninit = TiGetClient(sdTile);
|
|
arg.fra_region = (ExtRegion *) &ret;
|
|
arg.fra_each = SimTransistorTile;
|
|
(void) ExtFindNeighbors( sdTile, arg.fra_pNum, &arg );
|
|
|
|
/* Unmark the transitor, since its not part of this region */
|
|
arg.fra_region = (ExtRegion *) arg.fra_uninit;
|
|
arg.fra_uninit = (ClientData) &ret;
|
|
arg.fra_each = (int (*)()) NULL;
|
|
(void) ExtFindNeighbors( sdTile, arg.fra_pNum, &arg );
|
|
|
|
if( (tNum = SimTermNum( &transistor, reg )) < 0 )
|
|
{
|
|
TxPrintf( "\tSimFindOneNode: bad transistor terminal number\n" );
|
|
goto use_name;
|
|
}
|
|
|
|
ret.nd_name = SimTxtorLabel( tNum, &sx->scx_trans, &transistor );
|
|
ret.nd_what = ND_NAME;
|
|
}
|
|
else /* no transistors found, get the regions labels */
|
|
{
|
|
SimAddNodeList( reg );
|
|
SimAddDefList( def );
|
|
|
|
use_name:
|
|
ExtLabelOneRegion( def, ExtCurStyle->exts_nodeConn, reg );
|
|
ret.nd_region = reg;
|
|
ret.nd_what = ND_REGION;
|
|
}
|
|
return( &ret );
|
|
}
|
|
|
|
|
|
/*
|
|
*----------------------------------------------------------------
|
|
* SimGetNodeName
|
|
*
|
|
* This procedure uses the Magic circuit extraction code to generate
|
|
* the node name. The node is extracted by searching the database
|
|
* for all tiles electrically connected to the node. Each tile is
|
|
* marked with a pointer to the node region it belongs to. It is
|
|
* the node region data structure which contains the labels for a
|
|
* node. The "preferred" label for the node is taken, and this
|
|
* is combined with the path name to produce the complete node name.
|
|
*
|
|
* Results:
|
|
* A pointer to the node name is returned. This is a pointer to
|
|
* statically allocated memory, so subsequent calls to this procedure
|
|
* will change the node name the returned pointer references.
|
|
*
|
|
* Side effects:
|
|
* Any node region created is added to the node region list.
|
|
*----------------------------------------------------------------
|
|
*/
|
|
|
|
char *
|
|
SimGetNodeName(
|
|
SearchContext *sx, /* current search context */
|
|
Tile *tp, /* tile in this cell which is part
|
|
* of the node
|
|
*/
|
|
const char *path) /* path name of hierarchy of search */
|
|
{
|
|
NodeRegion *nodeList;
|
|
LabelList *ll;
|
|
static char nodename[256];
|
|
char buff[256];
|
|
char *text;
|
|
char *nname;
|
|
|
|
SimSawAbortString = FALSE;
|
|
|
|
if( SimUseCoords && simExtStyle != ExtCurStyle )
|
|
SimInitConnTables();
|
|
|
|
/* check to see if this tile has been extracted before */
|
|
|
|
if (TiGetClient(tp) == extUnInit)
|
|
{
|
|
NodeSpec *ns;
|
|
|
|
ns = SimFindOneNode(sx, tp);
|
|
if( ns->nd_what == ND_NAME )
|
|
{
|
|
SimSawAbortString = TRUE;
|
|
return( ns->nd_name );
|
|
}
|
|
nodeList = ns->nd_region;
|
|
}
|
|
else
|
|
{
|
|
nodeList = (NodeRegion *)TiGetClientPTR(tp);
|
|
}
|
|
|
|
/* generate the node name from the label region and the path name */
|
|
|
|
text = extNodeName((LabRegion *)nodeList);
|
|
strcpy(buff, text);
|
|
strcpy(nodename, path);
|
|
strcat(nodename, text);
|
|
|
|
/* check to see if we should abort the search on the node name */
|
|
|
|
if (!SimInitGetnode) {
|
|
if (HashLookOnly(&SimGetnodeTbl, buff) != (HashEntry *) NULL) {
|
|
SimSawAbortString = TRUE;
|
|
if (HashLookOnly(&SimAbortSeenTbl, buff) == (HashEntry *) NULL) {
|
|
HashFind(&SimAbortSeenTbl, buff);
|
|
TxPrintf("Node name search aborted on \"%s\"\n", buff);
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Check whether or not to print out node name aliases. Each alias
|
|
* found is hashed in a table in order to suppress printing of
|
|
* duplicate aliases.
|
|
*/
|
|
|
|
if (SimGetnodeAlias && SimIsGetnode) {
|
|
if (HashLookOnly(&SimGNAliasTbl, nodename) == (HashEntry *) NULL) {
|
|
HashFind(&SimGNAliasTbl, nodename);
|
|
#ifdef MAGIC_WRAPPER
|
|
Tcl_AppendElement(magicinterp, nodename);
|
|
#else
|
|
TxPrintf("alias: %s\n", nodename);
|
|
#endif
|
|
}
|
|
}
|
|
|
|
/* search the list of all labels for this node, creating the full
|
|
* node name and returning the "best" node name found.
|
|
*/
|
|
for (ll = nodeList->nreg_labels; ll; ll = ll->ll_next) {
|
|
if (ll->ll_label->lab_text == text) {
|
|
for (ll = ll->ll_next; ll; ll = ll->ll_next) {
|
|
nname = ll->ll_label->lab_text;
|
|
if (extLabType(nname, LABTYPE_NAME)) {
|
|
strcpy(nodename, path);
|
|
strcat(nodename, nname);
|
|
if (efPreferredName(nname, buff)) {
|
|
strcpy(buff, nname);
|
|
}
|
|
if (SimGetnodeAlias && SimIsGetnode) {
|
|
if (HashLookOnly(&SimGNAliasTbl, nodename)
|
|
== (HashEntry *) NULL) {
|
|
HashFind(&SimGNAliasTbl, nodename);
|
|
#ifdef MAGIC_WRAPPER
|
|
Tcl_AppendElement(magicinterp, nodename);
|
|
#else
|
|
TxPrintf("alias: %s\n", nodename);
|
|
#endif
|
|
}
|
|
}
|
|
}
|
|
}
|
|
break;
|
|
}
|
|
}
|
|
strcpy(nodename, path);
|
|
strcat(nodename, buff);
|
|
return(nodename);
|
|
}
|
|
|
|
/*
|
|
*----------------------------------------------------------------
|
|
* SimGetNodeCleanup
|
|
*
|
|
* This procedure is called to clean up the data structures and the
|
|
* tile database after a node name is extracted.
|
|
*
|
|
* Results:
|
|
* None.
|
|
*
|
|
* Side effects:
|
|
* The node region list and cell def lists are re-initialized.
|
|
*----------------------------------------------------------------
|
|
*/
|
|
|
|
void
|
|
SimGetNodeCleanUp(void)
|
|
{
|
|
SimFreeNodeRegs();
|
|
SimInitDefList();
|
|
}
|