153 lines
6.3 KiB
Groff
153 lines
6.3 KiB
Groff
.TH EXT2SPICE 1
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.UC 4
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.SH NAME
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ext2spice \- convert hierarchical \fIext\fR\|(5) extracted-circuit files
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to flat \fIspice\fR\| files
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.SH SYNOPSIS
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.B ext2spice
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[
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.B \-B
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] [
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.I "extcheck-options"
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] [
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.I -M|m
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] [
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.I -y num
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] [
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.I -f hspice|spice3|spice2
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] [
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.I -J hier|flat
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] [
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.I -j device:sdRclass[/subRclass]/defaultSubstrate
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]
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.I root
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.SH DESCRIPTION
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Ext2spice will convert an extracted circuit from the hierarchical
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\fIext\fR\|(5) representation produced by Magic to a flat spice
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file which can be accepted by spice2, spice3, hspice and other
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simulation tools.
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The root of the tree to be extracted is the file \fIroot\fB.ext\fR;
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it and all the files it references are recursively flattened.
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The result is a single, flat representation of the circuit that is
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written to the file \fIroot\fB.spice\fR .
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.LP
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The following options are recognized:
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.TP 1.0i
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.B \-o\ \fIoutfile\fP
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Instead of leaving output in the file \fIroot\fB.spice\fR, leave it
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in \fIoutfile\fP.
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.TP 1.0i
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.B \-B
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Don't output transistor or node attributes in the spice file.
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Usually the attributes of a node or a device are output as
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special comments **fetattr and **nodeatrr which can be processed
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further to create things such a initial conditions etc.
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.TP 1.0i
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.B \-F
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Don't output nodes that aren't connected to fets (floating nodes).
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Normally capacitance from these nodes is output with the comment
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**FLOATING attached on the same line.
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.TP 1.0i
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.B \-t\fIchar\fR
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Trim characters from node names when writing the output file.
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\fIChar\fR
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should be either "#" or "!".
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The option may be used twice if both characters
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are desired. Trimming "#" and "!" is enabled by default when the format is
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hspice.
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.TP 1.0i
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.B -\fIM|m\fR
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Merge parallel fets. \fI-m\fR means conservative merging of fets that have
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equal widths only (usefull with hspice format multiplier if delta W
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effects need to be taken care of). -M means aggressive merging: the fets
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are merged if they have the same terminals and the same length.
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.TP 1.0i
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.B \-y \fInum\fR
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Select the precision for outputing capacitors. The default is 1 which means
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that the capacitors will be printed to a precision of .1 fF.
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.TP 1.0i
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.B \-f \fIhspice|spice2|spice3\fR
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Select the output format. Spice3 is the the format understood by the
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latest version of berkeley spice. Node names have the same names as they
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would in a \fIsim\fR(5) file and no special constructs are used.
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Spice2 is the format understood by the older version of spice (which
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usually has better convergence). Node names are numbers and a dictionary
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of number and corresponding node is output in the end.
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HSPICE is a format understood by meta-software's hspice and other
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commercial tools. In this format node names cannot be longer than 15
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characters long (blame the fortran code): so if a hierarchical node name
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is longer it is truncated to something like x1234/name where x1234 is
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an alias of the normal node hierarchical prefix and name its hierarchical
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postfix (a dictionary mapping prefixes to real hierarchical paths is output
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at the end of the spice file). If the node name is still longer than 15
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characters long (again blame the fortran code) it is translated to something
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like z@1234 and the equivalent name is output as a comment. In addition since
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hspice supports scaling and multipliers so the output dimensions are in
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lambdas and if parallel fets are merged the hspice construct \fIM\fR is used.
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.TP 1.0i
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.B \-J \fIhier|flat\fR
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Select the source/drain area and perimeter extraction algorithm. If
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\fIhier\fR is selected then the areas and perimeters are extracted
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\fIonly within each subcell\fR. For each fet in a subcell the area
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and perimeter of its source and drain within this subcell are output.
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If two or more fets share a source/drain node then the total area and
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perimeter will be output in only one of them and the other will have 0.
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If \fIflat\fR is selected the same rules apply only that the scope of
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search for area and perimeter is the whole netlist. In general \fIflat\fR
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(which is the default) will give accurate results (it will take into
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account shared sources/drains) but hier is provided for backwards
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compatibility with version 6.4.5. On top of this selection you can
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individually control how a terminal of a specific fet will be extracted
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if you put a source/drain attribute. \fIext:aph\fR makes the extraction
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for that specific terminal hierarchical and \fIext:apf\fR makes the
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extraction flat (see the magic tutorial about attaching attribute labels).
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Additionaly to ease extraction of bipolar transistors the gate attribute
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\fIext:aps\fR forces the output of the substrate area and perimeter for
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a specific fet (in flat mode only).
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.TP 1.0i
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.B \-j \fIdevice:sdRclass[/subRclass]/defaultSubstrate\fR
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Gives ext2sim information about the source/drain resistance class of the
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fet type \fIdevice\fR. Makes \fIdevice\fR to have \fIsdRclass\fR source
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drain resistance class, \fIsubRclass\fR substrate (well) resistance class
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and the node named \fIdefaultSubstrate\fR as its default substrate.
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The defaults are nfet:0/Gnd\! and pfet:1/6/Vdd\! which correspond to the
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MOSIS technology file but things might vary in your site. Ask your local
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cad administrator.
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.PP
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The way the extraction of node area and perimeter works in magic the total
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area and perimeter of the source/drain junction is summed up on a single node.
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That is why all the junction areas and perimeters are summed up on a single
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node (this should not affect simulation results however).
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.PP
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\fISpecial care must be taken when the substrate of a fet is tied to a
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node other than the default substrate\fR (eg in a bootstraping charge
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pump).
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To get the correct substrate info in these cases the fet(s) with
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separate wells should be in their own separate subcell with ext:aph attributes
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attached to their sensitive terminals (also all the transistors which share
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sensistive terminals with these should be in another subcell with the same
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attributes).
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.PP
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In addition, all of the options of \fIextcheck\fR\|(1) are accepted.
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.PP
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The awk filter spice2sim is provided with the current distribution for
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debugging purposes.
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.SH "SEE ALSO"
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extcheck\|(1), ext2spice\|(1),
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magic\|(1), rsim\|(1), ext\|(5), sim\|(5)
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.SH AUTHOR
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Stefanos Sidiropoulos.
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.SH BUGS
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The areas and perimeters of fet sources and drains work only with the
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simple extraction algorith and not with the extresis flow. So you have
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to model them as linear capacitors (create a special extraction style)
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if you want to extract parasitic resistances with extresis.
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