184 lines
6.7 KiB
Groff
184 lines
6.7 KiB
Groff
.TH EXT2SIM 1
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.UC 4
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.SH NAME
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ext2sim \- convert hierarchical \fIext\fR\|(5) extracted-circuit files
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to flat \fIsim\fR\|(5) files
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.SH SYNOPSIS
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.B ext2sim
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[
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.B \-a
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.I aliasfile
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] [
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.B \-l
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.I labelsfile
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] [
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.B \-o
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.I simfile
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] [
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.B \-A
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] [
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.B \-B
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] [
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.B \-F
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] [
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.B \-L
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] [
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.B \-t
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] [
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.I "extcheck-options"
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] [
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.I -y num
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] [
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.I -f mit|lbl|su
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] [
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.I -J hier|flat
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] [
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.I -j device:sdRclass[/subRclass]/defaultSubstrate
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]
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.I root
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.SH DESCRIPTION
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Ext2sim will convert an extracted circuit from the hierarchical
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\fIext\fR\|(5) representation produced by Magic to the
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flat \fIsim\fR\|(5) representation required by many simulation tools.
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The root of the tree to be extracted is the file \fIroot\fB.ext\fR;
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it and all the files it references are recursively flattened.
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The result is a single, flat representation of the circuit that is
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written to the file \fIroot\fB.sim\fR, a list of node aliases
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written to the file \fIroot\fB.al\fR, and a list of the locations
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of all nodenames in CIF format, suitable for plotting, to the
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file \fIroot\fB.nodes\fR.
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The file \fIroot\fB.sim\fR is
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suitable for use with programs such as
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\fIcrystal\fP\|(1), \fIesim\fP\|(1), or \fIsim2spice\fP\|(1).
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.LP
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The following options are recognized:
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.TP 1.0i
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.B \-a\ \fIaliasfile\fP
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Instead of leaving node aliases in the file \fIroot\fB.al\fR, leave it
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in \fIaliasfile\fP.
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.TP 1.0i
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.B \-l\ \fIlabelfile\fP
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Instead of leaving a CIF file with the locations of all node names
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in the file \fIroot\fB.nodes\fR, leave it in \fIlabelfile\fP.
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.TP 1.0i
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.B \-o\ \fIoutfile\fP
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Instead of leaving output in the file \fIroot\fB.sim\fR, leave it
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in \fIoutfile\fP.
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.TP 1.0i
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.B \-A
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Don't produce the aliases file.
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.TP 1.0i
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.B \-B
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Don't output transistor or node attributes in the \fB.sim\fR file.
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This option will also disable the output of information such as
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the area and perimeter of source and drain diffusion and the
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fet substrate. For compatibitlity reasons the latest version of ext2sim
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outputs this information as node attibutes.
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This option is necessary when preparing input for programs that
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don't know about attributes, such as \fIsim2spice\fR\|(1) (which is
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actually made obsolete by \fIext2spice\fR\|(1), anyway),
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or \fIrsim\fR\|(1).
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.TP 1.0i
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.B \-F
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Don't output nodes that aren't connected to fets (floating nodes).
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.TP 1.0i
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.B \-L
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Don't produce the label file.
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.TP 1.0i
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.B \-t\fIchar\fR
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Trim characters from node names when writing the output file.
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\fIChar\fR
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should be either "#" or "!".
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The option may be used twice if both characters
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are desired.
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.TP 1.0i
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.B \-f \fIMIT|LBL|SU\fR
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Select the output format. MIT is the traditional \fIsim\fR(5) format.
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LBL is a variant of it understood by \fIgemini\fR(1) which includes the
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substrate connection as a fourth terminal before length and width.
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SU is the internal Stanford format which is described also in \fIsim\fR(5)
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and includes areas and perimeters of fet sources, drains and substrates.
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.TP 1.0i
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.B \-y \fInum\fR
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Select the precision for outputing capacitors. The default is 1 which means
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that the capacitors will be printed to a precision of .1 fF.
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.TP 1.0i
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.B \-J \fIhier|flat\fR
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Select the source/drain area and perimeter extraction algorithm. If
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\fIhier\fR is selected then the areas and perimeters are extracted
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\fIonly within each subcell\fR. For each fet in a subcell the area
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and perimeter of its source and drain within this subcell are output.
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If two or more fets share a source/drain node then the total area and
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perimeter will be output in only one of them and the other will have 0.
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If \fIflat\fR is selected the same rules apply only that the scope of
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search for area and perimeter is the whole netlist. In general \fIflat\fR
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(which is the default) will give accurate results (it will take into
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account shared sources/drains) but hier is provided for backwards
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compatibility with version 6.4.5. On top of this selection you can
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individually control how a terminal of a specific fet will be extracted
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if you put a source/drain attribute. \fIext:aph\fR makes the extraction
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for that specific terminal hierarchical and \fIext:apf\fR makes the
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extraction flat (see the magic tutorial about attaching attribute labels).
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Additionaly to ease extraction of bipolar transistors the gate attribute
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\fIext:aps\fR forces the output of the substrate area and perimeter for
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a specific fet (in flat mode only).
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.TP 1.0i
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.B \-j \fIdevice:sdRclass[/subRclass]/defaultSubstrate\fR
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Gives ext2sim information about the source/drain resistance class of the
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fet type \fIdevice\fR. Makes \fIdevice\fR to have \fIsdRclass\fR source
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drain resistance class, \fIsubRclass\fR substrate (well) resistance class
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and the node named \fIdefaultSubstrate\fR as its default substrate.
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The defaults are nfet:0/Gnd\! and pfet:1/6/Vdd\! which correspond to the
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MOSIS technology file but things might vary in your site. Ask your local
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cad administrator.
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.PP
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The way the extraction of node area and perimeter works in magic the total
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area and perimeter of the source/drain junction is summed up on a single node.
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That is why all the junction areas and perimeters are summed up on a single
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node (this should not affect simulation results however).
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.PP
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\fISpecial care must be taken when the substrate of a fet is tied to a
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node other than the default substrate\fR (eg in a bootstraping charge
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pump).
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To get the correct substrate info in these cases the fet(s) with
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separate wells should be in their own separate subcell with ext:aph attributes
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attached to their sensitive terminals (also all the transistors which share
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sensistive terminals with these should be in another subcell with the same
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attributes).
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.PP
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In addition, all of the options of \fIextcheck\fR\|(1) are accepted.
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.SH "SCALING AND UNITS"
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If all of the \fB.ext\fR files in the tree read by \fIext2sim\fP have the
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same geometrical scale (specified in the \fBscale\fP
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line in each \fB.ext\fR file),
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this scale is reflected through to the output, resulting in substantially
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smaller \fB.sim\fR files.
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Otherwise, the geometrical unit in the output \fB.sim\fR file
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is a centimicron.
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.PP
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Resistance and capacitance are always output in ohms and femptofarads,
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respectively.
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.SH "SEE ALSO"
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extcheck\|(1), ext2dlys\|(1), ext2spice\|(1),
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magic\|(1), rsim\|(1), ext\|(5), sim\|(5)
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.SH AUTHOR
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Walter Scott additions/fixes by Stefanos Sidiropoulos.
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.SH BUGS
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Transistor gate capacitance is typically not included in node
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capacitances, as most analysis tools compute the gate capacitance directly
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from the gate area.
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The \fB-c\fR flag therefore provides a limit only on non-gate capacitance.
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The areas and perimeters of fet sources and drains work only with the
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simple extraction algorith and not with the extresis flow. So you have
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to model them as linear capacitors (create a special extraction style)
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if you want to extract parasitic resistances with extresis.
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