"defaultareacap" and "defaultperimeter" statements in the technology
file. Now, the parser makes use of the configuration of the
substrate from the "substrate" line to generate a default list of
which types and planes represent the substrate, and which types and
planes represent shielding to the substrate. This solves an issue
with the use of substrate isolation layers (e.g., "isosub" in
sky130A), because its definition and usage created substrate shields
on two planes (well and dwell), while the syntax for "defaultareacap"
and "defaultperimeter" only allow one shielding plane to be defined.
that makes a net a global net if there is a Tcl variable of the
same name. This conflicts with a later use of Tcl variables VDD
and GND to denote power and ground names, which is a completely
different usage.
value 1 after finding a substrate connecting type shielded (by deep
nwell, in the example) from the substrate, thus preventing the
search from processing any remaining substrate types. Solved by
changing the return value to zero to keep the search going.
record to the label structure to hold the port number. One major
issue stemming from this was reported in github issue #203 by Anton
Blanchard. This commit fixes that error.
output for transistors. The problem came from a change made to
fix an issue with capacitors marked as floating nodes because some
nodes are not output as source or drain. But those nodes are output
before the parameters, so when generating parameter output, all
nodes appear to have already been output. Solution: Specify an
additional bit in the "visited" mask for the node having been output
that is separate from the mask for resist classes used by the code
that writes parameter values, and use that bit as a test for whether
the node is connected to some device (not necessarily a FET source
or drain).
used by "topVisit" and "subcktVisit" in ext2spice.c, probably
caused by having different names on the same port number, the
subcktVisit() routine was modified to use exactly the same
enumeration as topVisit() so that they are guaranteed to have
the same result.
this limited ports to 16384, which seemed reasonable at the time.
However, the sky130_sram_macro layouts connect power and ground in a
way that when coupled with "extract unique" can generate tens of
thousands of ports and overrun the bit field, showing that automation
can do the unexpected. The solution was to split out the port number
from the label record as its own 32-bit value.
have already been output; i.e., that have EF_PORT set. However,
since EF_PORT is now set on all implicit ports, it is likely that
this part of the code is no longer exercised at all, and may be
removed.
connections through the substrate as the same node, and so will
not force different nodes names on the soft connection to be
unique. This should probably be selectable behavior. However, as
written, the "extract" command will always merge soft connections,
so giving them unique names just causes problems with "extract".
issue at the change made in revision 214. This was done incorrectly
in two ways, one being a set of statements inside an if() block that
should have been executed always, and the other an incorrect use of
the EF_DEVTERM flag, setting it when it should not have been set.
implicit substrate connections under some conditions were not added
to the subcircuit pin list. When this was corrected, the call to
the subcircuit was missing the implicit substrate port. When that
was corrected, the implicit substrate port printed was the subcircuit's
local node name, not the connection from above in the hierarchy. The
underlying problem was that the substrate was marked as a port in a
node record that was in another (flattened and unused) def and so not
seen when enumerating the def's node list. It's possible that the
better solution is that the efNodeHashTable() should be enumerated to
write subcircuit ports, not def->def_nodes. However, now, by using
EFHNLook(), the corresponding entry in efNodeHashTable() is found and
used.
work around the issue of loading a file containing references to
cells with the same name as cells already loaded. This is probably
going to cause additional headaches until a proper checksum method
is implemented.
behave as one would expect; e.g., "cellname self" returns the name
of the currently edited cell if nothing is selected; "cellname
rename <name>" renames the currently edited cell to <name>.
Modified the "extract" command so that it will not extract a cell
named "(UNNAMED)" but will insist that the cell must be given a
proper name, much like the "writeall" command does.
rectangle. Likewise, this also fixes an unexpected result when
doing "spliterase" on a zero-area rectangle (which does not cause
a segfault, but is not what one would want magic to do).
when reading in a .mag file. The routine was not checking for
whether a "use" entry in the file was the first one encountered
or not. The path is only ever given for the first use of any cell
def, so for any cell after the first, the path should have already
been resolved. This fix avoids lots of unnecessary error messages
when reading a file in a different directory. Also, because the
routine now checks for the first use in a file, any error messages
that do occur will only be displayed for the first use, not all of
them.
statements, with all "hard" connections being enumerated in the
same PORT entry, and "soft" connections (same label on unconnected
areas; e.g., through substrate or resistor device) being
enumerated as separate PORT entries, per the LEF spec. Also
corrected behavior with respect to the "lef write -toplayer"
option, which was treating each port label independently, and so
generating entries for lower layers of a port if there were ports
on those layers, in contravention to the "-toplayer" option.
Also: Added the PINS section to the "def write" output; this had
been left as a "to be completed" item but was never done in spite
of being easy to add.
entries for "floating" labels. Otherwise it is possible for the
hierarchical checks to find the label in flattened geometry and
reference it, resulting in merge statements in an .ext file that
reference undeclared nodes, ultimately resulting in extflat
failing to perform the merge, and an incorrect netlist.
to not get into the subcircuit port list during ext2spice. The new
fix brings back (unfortunately) the behavior of creating a substrate
node for cells that have no substrate connection to any device;
this will have to be handled separately.
solution; it would be much better to make the value adjustible, but
the array of tiles sized to LAYERS_PER_CONTACT is a Region structure,
and the routine that frees the Region structures does not have a way
to call a routine to take additional measures like free'ing a sub-
structure of the Region. A proper solution will require some work.
commands on selections in a cell that is not editable. Moves
and Copies were already handled correctly; this correction fixes
Delete and transforms (e.g., rotates and flips).
messages which was traced to code that changes a drivepoint position
to match a label; the same drivepoint may be part of the record for
the initial position to search on the net, in which case if the
position is changed, then the tile type needs to be changed to match
the new position.
using qsort() instead of its own linked-list-based sorting, which
is horribly inefficient. This change allows power nets (which
tend to be connected to all transistors) to be extracted in a
reasonable amount of time (hours instead of days).
an optional extra argument to the "select" command that can be used
to select labels by glob-style matching; e.g., "select area labels
VSS*" or "select less area labels *_1". This will help in managing
labels after flattening a standard cell design; e.g., by using
"select less area labels */VDD".
to eliminate all redundant names resulting from redundant labels.
Changed the behavior of "goto" so that it will find local names with
slashes, which are the result of using "flatten". A hierarchical
search is done first, as before, but on failure to find a subcell
component, the local cell is searched for the verbatim name.
specific nets to extract, rather than excluding them. That allows
"extresist" to target specific nets like the power supply or a clock
tree for extraction.
wrong, and it needs revisiting. This is the cause of a number of
negative capacitances appearing in the netlist (even after accounting
for overlap with subcircuits).
all geometry will be handled; the previous behavior expected only
a single rectangle per pin and so would only acknowledge the last
entry in any list of rectangles for the pin.
actually an issue and probably never relevant. extresist now works
except for substrate connections and soft connections between substrate
regions. That will require additional coding, not bugfixing, so I'm
committing the last of this set of bugfixes before starting that.
"ext2sim extresist on", which was being shared; that leads to
confusion, especially when using "ext2sim" to generate a node
name input file for "extresist". Also: Added a warning when two
ports are merged in a .ext file, as this can lead to numerous
incorrect entries in netlist output.
text formatting. Made one critical correction to ResGetDevice() to
pass the device type; otherwise, devices on different planes (e.g.,
MiM caps) with the same coordinate will always return the device on
the lowest plane, leading to incorrect results and an eventual crash
when the device record is free'd twice.
support of devices with terminals on different plances, such as
capacitors, diodes, and bipolar transistors. Output now appears
to give meaningful results for flattened layouts, although
numerous issues remain for hierarchical layouts.
Tim Edwards