a long-standing error (introduced with the "extresist geometry"
option) that can cause nets not to be extracted (due to the first
record not having extraction data, which was itself a long-standing
error in the code but which was not fixed correctly); (2) handle
"device mosfet" type transistors (previously only handled the old
"fet" type extraction devices); and (3) correct for the res.ext
file having a different scalefactor relative to the .ext file. The
latter item was solved by forcing all input to scale like
ExtCurStyle->exts_unitsPerLambda, locally correcting all input as
needed. Note that extresist still needs to handle other extraction
devices (e.g., resistors and capacitors) but those will require
additional handling in the routines which analyze the current path
to determine how to break up wires into paths.
include (1) specification of sidewall or surface to use for
each type individually, rather than a single method for all
types, and (2) specification of a linear model R = Ax + B for
the ratio limit when diodes are attached to the wire, where x
is the diode surface area (unitless, as this is a ratio).
an existing cell. If the existing cell has labels but the labels
are defined as point labels (no rectangle defined using specific
layer-purpose pairs), then the LEF macro's port geometry will be
used for the labels. Because the GDS file can define label sizes
and fonts, which the LEF file cannot, but because the LEF file may
define multiple rectangles per port, the original point label is
given the first port rectangle from the LEF file, while the
remainder of the labels in the LEF file generate new non-rendered
labels in the cell.
which takes the existing generated CIF plane, finds all enclosed
areas that have an area less than <area>, and fills them in. This
satisfies a minimum hole area rule in a way that is not possible
with any of the existing CIF operators.
which adds an offset value of "start" to both X and Y from the
lower left corner of the fill area. This allows the use of the
"offset" (from the previous git commit) to be declared on different
layers without creating an exact overlap, as is often required by
foundries for fill patterns.
from a selection, which can then be used to index into other lists.
This lets one selection be made on a list of arbitrary names, and
then additional parameters can be linked together with the same
index). Also, implemented (finally!) the "offset" parameters of
the "slots" function (as advertised in the documentation).
like resistors where a tile other than space may border the resistor
device on its non-terminal sides (which is handled correctly, and
should not be considered an error).
remove redundant ports. A comment that I left in the code at the
last commit asked if it was necessary to call efAddNodes and
efAddConns recursively. An example came up in which the answer
is apparently "yes". These routines have been replaced by
efFlatNodes(), which appears to solve the problem. There is now
a question of whether efFlatNodesDeviceless() does anything, and
should its main behavior (to flag deviceless subcircuits) be
folded into efFlatNodes.
categorized by error type and scrolled through conveniently. However,
it needs work dealing with finding the actual error bounds. The
"DRC count" counts tiles, which is tile-plane-geometry-specific, and
"DRC listall why" fractures errors both over tiles and over the square
areas that the interactive DRC splits the layout into, for performance.
The DRC error plane needs to be changed to hold different types for
each error class, so that errors can be scanned by boundary instead of
by tile (work to be done).
rid of redundant port entries in subcircuits. There is still an outstanding
issue as to whether nodes and connections need to be recursively iterated
to the hierarchy bottom. The current fix corrected the test case. Also,
added a "-dereference" option to the "load" command to revert to the
original behavior of using only search paths from "addpath" when searching
for files to load.
by FIXED_BBOX derived from GDS and the new "boundary" cif input
rule, then the bbox property values take precedence over the
extent-of-geometry bounding box.
to multiple entries per device; the resistor length and width calculating
routine lost a break statement and would go into an infinite loop for
resistors with bends in them.
is placed over multiple types. This causes SelectChunk() to fail
and the pin will have no geometry output in the LEF file. To avoid
this, the area of the label is always painted into the select cell
so that if SelectChunk() fails, the label area still exists with
the label tile type.
(such as widespacing or directional surround) that will cause the
rule to be triggered without a cause due to a failure to reset the
error count from a previous triggered rule (the condition of failure
is much more rare than this explanation makes it sound, which is why
it went undiscovered for so long).
attached to a label in a GDS input file; the scalefactor that was
being used is reset at the beginning of a GDS read, and so becomes
invalid after a database rescaling, resulting in improperly scaled
label geometry if "gds read" is used more than once.
I understand the problem, which is that nodes are ordered according
to precedence of EFHNBest() within a circuit, but there is no
concept of ordering between circuits. So ports end up listing nodes
in arbitrary order, and the only way to resolve the order is to use
EFHNBest() as is done within a subcircuit. Appears to work for
different edge cases tested.
ports, to avoid creating ports for node names that are redundant.
It would probably be better to avoid creating the redundant node
names in the first place; however, I am less certain why these
are generated. The incorrect additional ports all have hierarchical
names in the cell, which is a sign that they are incorrect, as the
cell itself should not have any parents. The level of certainty
about this fix is definitely not 100%, but it was tested on a
hierarchical analog design, and setting levels of parasitic caps
caused new nodes to appear in subcircuits and in no cases did
information appear to be lost.
with ext2spice without the hierarchy option. More work needed to
produce correct hierarchical output and to support extraction
devices other than the old "fet" record.
it only complains about (i.e., issues an error message) ports with
the same index but different text, indicating a read port number
collision and a true error.
the below-threshold coupling caps being removed from the hierarchy,
added code to suppress the error message when it is clearly related
to a below-threshold cap that has been removed.
used with "ext2spice hierarchy on" because the device index is not
reset between calls to output cells in the hierarchy, leading to
a mismatch of the index for all cells after the first one output.
checks. Added new command "antennacheck" and a routine that
adds feedback entries where violations are found. Extended the
syntax of the extraction section of the techfile to support the
antenna ratios and antenna calculation methods.
simple FET device in extresist. Also: Extended the bloat-all CIF operator
again, allowing the trigger layer for the bloat operation to include both
CIF layers and magic layers (previously only magic layers were supported).
This extension is possible due to the previous extension allowing the
trigger layer and bloating layers to be on separate planes. This operator
extension is useful for tagging geometry that is in the proximity of, but
not overlapping, geometry on another plane.
error whenever there are no DRC-CIF rules in the techfile. The
same error will be raised anyway when reading the techfile if
DRC-CIF rules are declared without a style being specified.
to be scaled down by "reducer" like all other values in the cell.
Suggests a need to have property types other than string, so that
a property type "rect" or "box" can be declared that is saved as a
Rect and always scales without special hack handling of the specific
string FIXED_BBOX. . .
reduction of memory and startup time, which was to maintain only
one CIF style in memory. The new method is just to read in and
keep the DRC CIF style separately from the output CIF style.
Because the CIF sections of the techfile are read before the DRC
sections, and the CIF DRC style is declared in the DRC section,
the CIF DRC style is read in on the fly during the first DRC
checking.
hierarchical cells (namely a scaling issue with .sim file units).
More can be done to make the extresist command more user friendly,
but at least port connections as drivers appears to work.
perimeter were not output because of recent code that broke the
routine that assigns the resistance classes to devices. This is
now fixed. Thanks to Dan Moore for bringing this to my attention,
and debugging investigations.
device type so that it is now properly backwards compatible with
the old-style "fet" records. Also corrected the record matching
such that it properly matches according to the number of terminals
while allowing the traditional interpretation that there may be
fewer S/D type records than terminals if the S/D types are the
same for all terminals.
function was used (HashFind, which never returns NULL, vs.
HashLookOnly, which does) resulting in a failure to solve the
problem which was being patched, which was ext2spice crashing
when cell arrays are present, which itself was due to allowing
brackets in base cell use names.
Tim Edwards