magic crashed when the conSrArea array exceeded the size of a 32-bit
int during the antenna rule check. Should be good for another four
orders of magnitude.
the last couple of days, was left in a state where it keeps appending
".mag" to the filename if "save" or "writeall" is executed more than
once in the same edit session. Also, added ext2sim.sh and ext2spice.sh
to the CLEANS list in tcltk, and added both to .gitignore so they are
not tracked. Removed them from git to stop the current tracking.
where the function drcFindOtherCells() was missing, which causes
interaction areas to be missed and messes up the DRC checks between
parent and child cells.
Conflicts:
VERSION
Merged recent changes from master back into bplane, as the efficiency of
bplane for doing extraction on large layouts is unquestionably better.
Fixed the implementation of DBMoveCell() for bplane. Corrected an error
in the bplane version of dbScaleCell() that enumerates cell uses but
does not free the list.
as an optional argument (which it is), and so defaults were not
applied, potentially leading to the wrong number of rows/columns in
a generated via if ROWCOL is not present in the DEF file.
of the pin port geometry and using those areas to create the
spacing between them and the obstruction layer. Otherwise, the
existing method used different databases (source vs. flattened) to
find the pin area, and they did not always agree on the exact
dimensions, leading to spacing errors within the LEF view.
than one name, because in that case one of the port records ends
up with a null pointer to a node, and causes a crash condition.
This can happen inadvertently, as when a connected node is not
specifically designated a port, but is forced to be a port
because of the connection.
coordinate system origin to the specified (current) location.
This is a much more efficient method than selecting everything in
a layout and moving it, especially for very large layouts where
selection and moving becomes prohibitive.
generating duplicate devices that may have parts overlaid in
different subcells; this failed to filter the check by plane of
the device, and so if any two devices exist at the same point in
two different planes (e.g., metal resistor and a transistor), one
of them would get eliminated.
Conflicts:
VERSION
calma/Depend
cif/Depend
cmwind/Depend
commands/Depend
database/Depend
dbwind/Depend
debug/Depend
drc/Depend
ext2sim/Depend
ext2spice/Depend
extflat/Depend
extract/Depend
garouter/Depend
gcr/Depend
graphics/Depend
grouter/Depend
irouter/Depend
lef/Depend
lisp/Depend
mzrouter/Depend
netmenu/Depend
plot/Depend
plow/Depend
resis/Depend
router/Depend
select/Depend
sim/Depend
tcltk/Depend
textio/Depend
tiles/Depend
utils/Depend
windows/Depend
wiring/Depend
Merged recent changes from master branch into bplane branch. Testing the
bplane implementation which has about a 5x improvement in extraction times
for large layouts, which is significant enough to move ahead with the bplane
implementation; however, the bplane implementation has not been thoroughly
vetted yet, so it will remain a branch until such time that it has been
validated.
multiple ports; also, when using the "-hide" option, the obstruction
area is computed from layer geometry, not from the bounding box.
Still left to do: Ensure minimum width on pins, and remove slivers
of obstruction that are below minimum width.
Tim Edwards