"ext2sim extresist on", which was being shared; that leads to
confusion, especially when using "ext2sim" to generate a node
name input file for "extresist". Also: Added a warning when two
ports are merged in a .ext file, as this can lead to numerous
incorrect entries in netlist output.
implements a method for handling ports in a subcircuit that have different
port names and indexes but are shorted together. "none" is the default
and backwards-compatible behavior that merges ports together, which will
often cause one of the ports to be optimized out of the netlist. "resistor"
will separate the port names with a 0-ohm ideal resistor. "voltage" will
separate the port names with a 0-volt voltage source. This should work
well for simulation and potentially for LVS, although its impact on LVS
has not been fully investigated.
the last commit, unfortunately. Thanks to Matt Guthaus for alerting me
to this. Also updated parts of the extresist code that remove the
dependence on ResConDCS; this is a minor update and should not affect
the operation of extresist. It is preparatory to doing more work to
support additional device types like capacitors, bipolars, and diodes.
code from extflat from type unsigned long to type TileTypeBitMask.
This increases the number of types of each to 256 and tracks the
number of types, so it should be difficult to exceed this amount.
commit, mostly relating to the scale of values in the ".nodes" file
produced by ext2sim. Making this file CIF syntax seemed unnecessary,
so I removed the CIF syntax and scaling. "extresist" can now produce
an apparently valid output on a standard cell layout. Even with the
change, the extresist output is still only pseudo-hierarchical, so
this does not preclude the need for eliminating the .sim format file
in favor of the .ext file, but it provides a working intermediate
form.
types and substrate connections. This is an intermediate step to
switching from a sim file format to an ext file format for input,
but resolves the worst issues of having the sim file not recognize
the devices or the substrate nodes. Implemented by using the sim
subcircuit format introduced in IRSIM with the "user subcircuit"
package. Implementation unfinished (work in progress).
p device; this was previously dependent only on the first character
of the extracted device model name. Since the tech file has control
over what the device layer names are but not the extracted model
names, the device layer type name is used as a backup way to determine
if the type is n or p, if that cannot be determined from the extracted
model name.
support asymmetric FETs and other devices like bipolars that have
three distinct terminals. This does not go as far as it should to
make the array independent of the number of declared terminals of
the device. However, it suffices to make, e.g., parameter "a2=area"
work for a bipolar device, and to generate the right drain and source
areas and perimeters for asymmetric (e.g., extended-drain) devices.
change from passing the HierName to passing the HierContext (of which
HierName is a part) so that more information from HierContext (such
as the cell use being visited) can be passed to the callback
procedure (largely for diagnostic purposes).
Tim Edwards