64 because I overran the 64 array with too many resistclasses in
a techfile. This really should be dynamically allocated; this
requires parsing the line to count tokens and reallocating as
needed (to be done).
a scaling issue in extract) which was caused by the addition of
hierarchical netlist generation. Finding hierarchical connections
requires finding instances by name, so it is vastly better to create a
hash table of instances instead of a linked list.
added a long time ago, since capacitors use a different method for
calculating width and length than either transistors or resistors,
so subcircuits need a special class designator or else the extraction
may calculate the wrong dimensions for device width by totalling the
perimeter between the device and terminal types, as it would for a
MOSFET.
8.2.74. Top-level port names are now flagged independently of
any subcircuit port, so they are easier to identify when determining
naming precedence for the net. This makes the code cleaner and
removes the problems arising from non-top-level ports and global
names overriding the subcircuit port names.
symmetric with writing them. Since the writing of .ext files
was changed to preferably use the location of the cell being
read, and since the extflat database does not save this path
information, it was necessary to check the main database entry
for each cell to determine if there is a non-default path where
the .ext file may have been saved (with the current working
directory used as a fall-back if the directory is not writeable).
development had been halted since it was first created back in April.
Version 8.2 is now the official development version, with the first
development push to create a Cairo graphics interface.
Tim Edwards