which adds an offset value of "start" to both X and Y from the
lower left corner of the fill area. This allows the use of the
"offset" (from the previous git commit) to be declared on different
layers without creating an exact overlap, as is often required by
foundries for fill patterns.
from a selection, which can then be used to index into other lists.
This lets one selection be made on a list of arbitrary names, and
then additional parameters can be linked together with the same
index). Also, implemented (finally!) the "offset" parameters of
the "slots" function (as advertised in the documentation).
like resistors where a tile other than space may border the resistor
device on its non-terminal sides (which is handled correctly, and
should not be considered an error).
remove redundant ports. A comment that I left in the code at the
last commit asked if it was necessary to call efAddNodes and
efAddConns recursively. An example came up in which the answer
is apparently "yes". These routines have been replaced by
efFlatNodes(), which appears to solve the problem. There is now
a question of whether efFlatNodesDeviceless() does anything, and
should its main behavior (to flag deviceless subcircuits) be
folded into efFlatNodes.
categorized by error type and scrolled through conveniently. However,
it needs work dealing with finding the actual error bounds. The
"DRC count" counts tiles, which is tile-plane-geometry-specific, and
"DRC listall why" fractures errors both over tiles and over the square
areas that the interactive DRC splits the layout into, for performance.
The DRC error plane needs to be changed to hold different types for
each error class, so that errors can be scanned by boundary instead of
by tile (work to be done).
rid of redundant port entries in subcircuits. There is still an outstanding
issue as to whether nodes and connections need to be recursively iterated
to the hierarchy bottom. The current fix corrected the test case. Also,
added a "-dereference" option to the "load" command to revert to the
original behavior of using only search paths from "addpath" when searching
for files to load.
by FIXED_BBOX derived from GDS and the new "boundary" cif input
rule, then the bbox property values take precedence over the
extent-of-geometry bounding box.
to multiple entries per device; the resistor length and width calculating
routine lost a break statement and would go into an infinite loop for
resistors with bends in them.
is placed over multiple types. This causes SelectChunk() to fail
and the pin will have no geometry output in the LEF file. To avoid
this, the area of the label is always painted into the select cell
so that if SelectChunk() fails, the label area still exists with
the label tile type.
(such as widespacing or directional surround) that will cause the
rule to be triggered without a cause due to a failure to reset the
error count from a previous triggered rule (the condition of failure
is much more rare than this explanation makes it sound, which is why
it went undiscovered for so long).
attached to a label in a GDS input file; the scalefactor that was
being used is reset at the beginning of a GDS read, and so becomes
invalid after a database rescaling, resulting in improperly scaled
label geometry if "gds read" is used more than once.
I understand the problem, which is that nodes are ordered according
to precedence of EFHNBest() within a circuit, but there is no
concept of ordering between circuits. So ports end up listing nodes
in arbitrary order, and the only way to resolve the order is to use
EFHNBest() as is done within a subcircuit. Appears to work for
different edge cases tested.
ports, to avoid creating ports for node names that are redundant.
It would probably be better to avoid creating the redundant node
names in the first place; however, I am less certain why these
are generated. The incorrect additional ports all have hierarchical
names in the cell, which is a sign that they are incorrect, as the
cell itself should not have any parents. The level of certainty
about this fix is definitely not 100%, but it was tested on a
hierarchical analog design, and setting levels of parasitic caps
caused new nodes to appear in subcircuits and in no cases did
information appear to be lost.
with ext2spice without the hierarchy option. More work needed to
produce correct hierarchical output and to support extraction
devices other than the old "fet" record.
it only complains about (i.e., issues an error message) ports with
the same index but different text, indicating a read port number
collision and a true error.
Tim Edwards