this limited ports to 16384, which seemed reasonable at the time.
However, the sky130_sram_macro layouts connect power and ground in a
way that when coupled with "extract unique" can generate tens of
thousands of ports and overrun the bit field, showing that automation
can do the unexpected. The solution was to split out the port number
from the label record as its own 32-bit value.
have already been output; i.e., that have EF_PORT set. However,
since EF_PORT is now set on all implicit ports, it is likely that
this part of the code is no longer exercised at all, and may be
removed.
issue at the change made in revision 214. This was done incorrectly
in two ways, one being a set of statements inside an if() block that
should have been executed always, and the other an incorrect use of
the EF_DEVTERM flag, setting it when it should not have been set.
implicit substrate connections under some conditions were not added
to the subcircuit pin list. When this was corrected, the call to
the subcircuit was missing the implicit substrate port. When that
was corrected, the implicit substrate port printed was the subcircuit's
local node name, not the connection from above in the hierarchy. The
underlying problem was that the substrate was marked as a port in a
node record that was in another (flattened and unused) def and so not
seen when enumerating the def's node list. It's possible that the
better solution is that the efNodeHashTable() should be enumerated to
write subcircuit ports, not def->def_nodes. However, now, by using
EFHNLook(), the corresponding entry in efNodeHashTable() is found and
used.
previous commit and can cause ports in the SPICE netlist to have
names other than what the port label declared. Expected not to be
fatal to the netlist, but it's a bit difficult to work with a
subcircuit that doesn't have the expected pin names.
that commit claimed to correct an issue with implicit ports not being
output, the solution often failed to properly assign the port number,
so while the implicit ports were added to the subcircuit definition,
they were often missing from the subcircuit call.
very long time but never discovered; in which any implicit port
connection into a subcell (that is otherwise labeled with ports) that
appears at the end of the node list (i.e., after all the declared
ports), will not be output, either in the subcircuit definition or
calls.
implements a method for handling ports in a subcircuit that have different
port names and indexes but are shorted together. "none" is the default
and backwards-compatible behavior that merges ports together, which will
often cause one of the ports to be optimized out of the netlist. "resistor"
will separate the port names with a 0-ohm ideal resistor. "voltage" will
separate the port names with a 0-volt voltage source. This should work
well for simulation and potentially for LVS, although its impact on LVS
has not been fully investigated.
code from extflat from type unsigned long to type TileTypeBitMask.
This increases the number of types of each to 256 and tracks the
number of types, so it should be difficult to exceed this amount.
characters. Instead of removing the non-alphanumeric characters, magic
now prepends an "x" to the name. Since this naming restriction does not
necessarily impact, say, LVS, it would probably be better to let this
behavior be enabled or disabled by a command.
area and perimeter across devices. The distributed allocation
was missing for hierarchical output, and the function that
accumulates values per resistance class was initializing by
iterating over device classes, not resistance classes, leading
to a segfault if the number of device classes is larger than the
number of resistance classes.
This reverts commit 46baae0ce6.
Reverting the last commit, as it does not work completely the way it
is supposed to, and will most likely have to be done in a different
way.
array delimiters and hierarchy separators (characters '/', '[', and ']')
that are part of instances or labels passed to magic, are preserved
from input to output, but internally marked (with a backslash escape)
so that they are not misinterpreted my magic when running ext2spice.
tech file format "version" section. This can be used to specify the
version of magic that must be used to be compatible with the tech file.
This effectively supercedes the technology version number. (2) Changed
the behavior of "make" to set the version and revision numbers on doing
"make" instead of "configure". This allows the version to update
correctly after doing a "git pull" followed by "make" without doing
"configure" in between. (3) Fixed a couple of issues that were flagged
as compile-time warnings.
could have multiple ports of the same name. This problem had been
worked over before, but there was an indpendent mechanism producing
the same result for a completely different reason, caused by subcells
being much larger than the cookie-cutter extraction method's extraction
regions. Solved by tracking port names in a hash table and preventing
re-use. (2) ext2spice was producing "no such node" errors; like (1)
this had been previously worked on, and like (1) this mechanism was
independent. Problem came from not passing -1 to extHierSubstrate for
the non-arrayed dimension of a 1-dimensional array. Also: Removed
the word "fatal" from extraction error reporting, as nearly all
extraction errors are entirely benign. This should clear up confusion
among alarmed end-users.
p device; this was previously dependent only on the first character
of the extracted device model name. Since the tech file has control
over what the device layer names are but not the extracted model
names, the device layer type name is used as a backup way to determine
if the type is n or p, if that cannot be determined from the extracted
model name.
support asymmetric FETs and other devices like bipolars that have
three distinct terminals. This does not go as far as it should to
make the array independent of the number of declared terminals of
the device. However, it suffices to make, e.g., parameter "a2=area"
work for a bipolar device, and to generate the right drain and source
areas and perimeters for asymmetric (e.g., extended-drain) devices.
"msubcircuit" extraction model, which would normally not make any
difference except that when source and/or drain are tagged with
terminal attributes, then the source and drain are swapped with
respect to what is expected in the output SPICE netlist.
change from passing the HierName to passing the HierContext (of which
HierName is a part) so that more information from HierContext (such
as the cell use being visited) can be passed to the callback
procedure (largely for diagnostic purposes).
than one name, because in that case one of the port records ends
up with a null pointer to a node, and causes a crash condition.
This can happen inadvertently, as when a connected node is not
specifically designated a port, but is forced to be a port
because of the connection.
order of layers than specified in the LEF/DEF spec. It is not clear
whether this is common practice, or a bug in the tool that produced the
DEF file that prompted this change. NOTE: The "grow" function applied
in this case should be replaced by the actual GDS input rule sequence,
that includes the grow and shrink merge. Otherwise, vias read from
DEF files do not match the layout from those read from GDS, even though
the mask layers represented by the layouts are the same.
views. Because the abstract view does not necessarily represent
actual connectivity, rely on the port indexes in the .ext file
to determine the number of ports and port order. Do not use
SpiceNodeName() to look up the node name, or unique ports that
are deemed shorted will go missing. Also: Modified the read-in
of .ext files so that use names may contain backslashes. Only
backslashes that end a line will be handled differently.
I understand the problem, which is that nodes are ordered according
to precedence of EFHNBest() within a circuit, but there is no
concept of ordering between circuits. So ports end up listing nodes
in arbitrary order, and the only way to resolve the order is to use
EFHNBest() as is done within a subcircuit. Appears to work for
different edge cases tested.
ports, to avoid creating ports for node names that are redundant.
It would probably be better to avoid creating the redundant node
names in the first place; however, I am less certain why these
are generated. The incorrect additional ports all have hierarchical
names in the cell, which is a sign that they are incorrect, as the
cell itself should not have any parents. The level of certainty
about this fix is definitely not 100%, but it was tested on a
hierarchical analog design, and setting levels of parasitic caps
caused new nodes to appear in subcircuits and in no cases did
information appear to be lost.
used with "ext2spice hierarchy on" because the device index is not
reset between calls to output cells in the hierarchy, leading to
a mismatch of the index for all cells after the first one output.
device type so that it is now properly backwards compatible with
the old-style "fet" records. Also corrected the record matching
such that it properly matches according to the number of terminals
while allowing the traditional interpretation that there may be
fewer S/D type records than terminals if the S/D types are the
same for all terminals.
the compiler. Some are obscure functions (plot verstatec hasn't
been used in years) but others (like SPICE distributed junctions)
are potentially significant sources of unexpected crashes on
systems that don't zero uninitialized memory.
64 because I overran the 64 array with too many resistclasses in
a techfile. This really should be dynamically allocated; this
requires parsing the line to count tokens and reallocating as
needed (to be done).
name-to-number mapping used for the HSPICE format between
subcircuits. Otherwise, subcircuits with the same instance ID
remain in the table and may cause nodes to be output with a name
that collides with other names in the same subcircuit. This only
affects output in HSPICE format.
all the settings normally used for LVS (hierarchy on, cthresh
infinite, subcircuit top auto, etc.). (2) Extract and extract
unique ignore cells marked as abstract views (property LEFview
is set) when checking for unconnected nets with the same name
label.
added a long time ago, since capacitors use a different method for
calculating width and length than either transistors or resistors,
so subcircuits need a special class designator or else the extraction
may calculate the wrong dimensions for device width by totalling the
perimeter between the device and terminal types, as it would for a
MOSFET.
Tim Edwards
Jan Belohoubek
Dan Moore