Additional extensions to allow "extend" to be used for transistor
gates when the gate length minimum may be larger than the gate width minimum, and to implement an "angles" option on the "width" rule that can implement rules where a layer width must be wider as measured from angled edges than from straight edges.
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@ -1043,7 +1043,7 @@ DRCTechAddRule(sectionName, argc, argv)
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"step_size",
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"surround", 6, 6, drcSurround,
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"layers1 layers2 distance presence why",
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"width", 4, 4, drcWidth,
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"width", 4, 5, drcWidth,
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"layers width why",
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"widespacing", 7, 8, drcSpacing,
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"layers1 width layers2 separation adjacency why",
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@ -1111,13 +1111,13 @@ DRCTechAddRule(sectionName, argc, argv)
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* Process an extension rule.
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* This is of the form:
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*
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* extend layers1 layers2 distance [exact_width] why
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* extend layers1 layers2 distance [exact_width | exclusive] why
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*
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* indicating that if "layers1" extends from "layers2", then it must
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* have a width of at least "distance". This is very much like the
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* "overhang" rule, except that the extension is optional. Example:
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*
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* extend nfet ndiff 2 "n-transistor length must be at least 2"
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* extend nfet *poly 3 "n-transistor width must be at least 3"
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*
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* "extend" implements the following general-purpose edge rule:
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*
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@ -1127,6 +1127,13 @@ DRCTechAddRule(sectionName, argc, argv)
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* maximum extension at distance. This is intended for use with, for
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* example, a fixed gate length for a specific type of device.
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*
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* Option "exclusive" is for use for, e.g., transistor length when the
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* length rule is larger than the minimum width rule. However, without
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* the option, "extend" sets OKtypes to the union of layers1 and layers2;
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* that covers, e.g., extension of diffusion from a gate where an
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* additional gate within the distance does not violate the rule. With
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* "exclusive", layers2 may not appear within "distance" of the edge.
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*
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* Results:
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* Returns distance.
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*
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@ -1152,12 +1159,18 @@ drcExtend(argc, argv)
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TileTypeBitMask set2, setZ, setN, setM;
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PlaneMask pMask1, pMask2, pset, ptest;
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bool exact = FALSE;
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bool exclusive = FALSE;
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if (!strncmp(argv[4], "exact_", 6))
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{
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exact = TRUE;
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why = drcWhyCreate(argv[5]);
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}
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else if (!strncmp(argv[4], "exclu", 5))
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{
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exclusive = TRUE;
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why = drcWhyCreate(argv[5]);
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}
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else
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why = drcWhyCreate(argv[4]);
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@ -1181,9 +1194,12 @@ drcExtend(argc, argv)
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return (0);
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}
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/* setM is the union of set1 and set2 */
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/* setM is the union of set1 and set2 unless exclusive == TRUE */
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TTMaskZero(&setM);
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TTMaskSetMask3(&setM, &set1, &set2);
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if (exclusive)
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TTMaskSetMask(&setM, &set1);
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else
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TTMaskSetMask3(&setM, &set1, &set2);
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/* setN is the inverse of set1, and setC is the inverse of set2 */
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TTMaskCom2(&setN, &set1);
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@ -1284,12 +1300,16 @@ drcExtend(argc, argv)
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* Process a width rule.
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* This is of the form:
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*
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* width layers distance why
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* width layers distance [angles] why
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*
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* e.g,
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*
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* width poly,pmc 2 "poly width must be at least 2"
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*
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* The option "angles" is computed only on non-manhattan edges and is used
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* in cases were, for example, an angled transistor has a minimum width
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* larger than that of a straight gate.
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*
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* Results:
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* Returns distance.
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*
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@ -1306,12 +1326,20 @@ drcWidth(argc, argv)
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{
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char *layers = argv[1];
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int distance = atoi(argv[2]);
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int why = drcWhyCreate(argv[3]);
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int why;
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TileTypeBitMask set, setC;
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PlaneMask pmask, pset, ptest;
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DRCCookie *dp, *dpnew;
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TileType i, j;
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int plane;
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int plane, flags = 0;
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if (!strncmp(argv[3], "angle", 5))
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{
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flags = DRC_SPLITTILE;
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why = drcWhyCreate(argv[4]);
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}
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else
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why = drcWhyCreate(argv[3]);
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ptest = DBTechNoisyNameMask(layers, &set);
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pmask = CoincidentPlanes(&set, ptest);
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@ -1344,7 +1372,7 @@ drcWidth(argc, argv)
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dp = drcFindBucket(i, j, distance);
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dpnew = (DRCCookie *)mallocMagic(sizeof (DRCCookie));
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drcAssign(dpnew, distance, dp->drcc_next, &set, &set,
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why, distance, DRC_FORWARD, plane, plane);
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why, distance, DRC_FORWARD | flags, plane, plane);
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dp->drcc_next = dpnew;
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}
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@ -1366,7 +1394,6 @@ drcWidth(argc, argv)
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plane, plane);
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dp->drcc_next = dpnew;
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}
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}
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}
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}
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