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magic
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Separated out the flag used for "ext2spice extresist on" and 

"ext2sim extresist on", which was being shared;  that leads to
confusion, especially when using "ext2sim" to generate a node
name input file for "extresist".  Also:  Added a warning when two
ports are merged in a .ext file, as this can lead to numerous
incorrect entries in netlist output.
This commit is contained in:
Tim Edwards 2021-09-13 10:36:01 -04:00
parent 2eb47969c7
commit c7077d38c3
3 changed files with 16 additions and 11 deletions
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2
VERSION
View File

@ -1 +1 @@
8.3.206 8.3.207

19
ext2sim/ext2sim.c
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@ -54,7 +54,6 @@ int simmergeVisit();
/* Options specific to ext2sim */ /* Options specific to ext2sim */
#ifdef EXT2SIM_AUTO #ifdef EXT2SIM_AUTO
bool esDoExtResis = FALSE;
bool esDevNodesOnly = FALSE; bool esDevNodesOnly = FALSE;
bool esNoAttrs = FALSE; bool esNoAttrs = FALSE;
bool esHierAP = FALSE; bool esHierAP = FALSE;
@ -63,7 +62,6 @@ bool esMergeDevsC = FALSE; /* merge devices of equal length & width */
int esCapAccuracy = 1; int esCapAccuracy = 1;
#else #else
extern bool esDoExtResis;
extern bool esDevNodesOnly; extern bool esDevNodesOnly;
extern bool esNoAttrs; extern bool esNoAttrs;
extern bool esHierAP; extern bool esHierAP;
@ -72,6 +70,7 @@ extern bool esMergeDevsC;
extern int esCapAccuracy; extern int esCapAccuracy;
#endif #endif
bool esDoSimExtResis = FALSE;
bool esNoAlias = TRUE; bool esNoAlias = TRUE;
bool esNoLabel = TRUE; bool esNoLabel = TRUE;
char simesDefaultOut[FNSIZE]; char simesDefaultOut[FNSIZE];
@ -323,15 +322,15 @@ CmdExtToSim(w, cmd)
case EXTTOSIM_EXTRESIST: case EXTTOSIM_EXTRESIST:
if (cmd->tx_argc == 2) if (cmd->tx_argc == 2)
{ {
Tcl_SetResult(magicinterp, (esDoExtResis) ? "on" : "off", NULL); Tcl_SetResult(magicinterp, (esDoSimExtResis) ? "on" : "off", NULL);
return; return;
} }
else if (cmd->tx_argc != 3) else if (cmd->tx_argc != 3)
goto usage; goto usage;
idx = Lookup(cmd->tx_argv[2], yesno); idx = Lookup(cmd->tx_argv[2], yesno);
if (idx < 0) goto usage; if (idx < 0) goto usage;
else if (idx < 3) esDoExtResis = TRUE; else if (idx < 3) esDoSimExtResis = TRUE;
else esDoExtResis = FALSE; else esDoSimExtResis = FALSE;
break; break;
case EXTTOSIM_ALIAS: case EXTTOSIM_ALIAS:
if (cmd->tx_argc == 2) if (cmd->tx_argc == 2)
@ -522,13 +521,13 @@ runexttosim:
if (simesOutName == simesDefaultOut) if (simesOutName == simesDefaultOut)
(void) sprintf(simesDefaultOut, "%s%s.sim", inName, (void) sprintf(simesDefaultOut, "%s%s.sim", inName,
((esDoExtResis) ? ".ext" : "")); ((esDoSimExtResis) ? ".ext" : ""));
if (esAliasName == esDefaultAlias) if (esAliasName == esDefaultAlias)
(void) sprintf(esDefaultAlias, "%s%s.al", inName, (void) sprintf(esDefaultAlias, "%s%s.al", inName,
((esDoExtResis) ? ".ext" : "")); ((esDoSimExtResis) ? ".ext" : ""));
if (esLabelName == esDefaultLabel) if (esLabelName == esDefaultLabel)
(void) sprintf(esDefaultLabel, "%s%s.nodes", inName, (void) sprintf(esDefaultLabel, "%s%s.nodes", inName,
((esDoExtResis) ? ".ext" : "")); ((esDoSimExtResis) ? ".ext" : ""));
if ((esSimF = fopen(simesOutName, "w")) == NULL) if ((esSimF = fopen(simesOutName, "w")) == NULL)
{ {
char *tclres = Tcl_Alloc(128); char *tclres = Tcl_Alloc(128);
@ -557,7 +556,7 @@ runexttosim:
} }
/* Read the hierarchical description of the input circuit */ /* Read the hierarchical description of the input circuit */
if (EFReadFile(inName, FALSE, esDoExtResis, FALSE) == FALSE) if (EFReadFile(inName, FALSE, esDoSimExtResis, FALSE) == FALSE)
{ {
EFDone(); EFDone();
return /* TCL_ERROR */; return /* TCL_ERROR */;
@ -734,7 +733,7 @@ main(argc, argv)
} }
/* Read the hierarchical description of the input circuit */ /* Read the hierarchical description of the input circuit */
if (EFReadFile(inName, FALSE, esDoExtResis, FALSE) == FALSE) if (EFReadFile(inName, FALSE, esDoSimExtResis, FALSE) == FALSE)
{ {
exit(1); exit(1);
} }

6
extflat/EFbuild.c
View File

@ -506,6 +506,12 @@ efBuildEquiv(def, nodeName1, nodeName2)
freeMagic(argv[7]); freeMagic(argv[7]);
return; return;
} }
else
{
/* Flag a strong warning */
TxError("Warning: Ports \"%s\" and \"%s\" are electrically shorted.\n",
nodeName1, nodeName2);
}
} }
/* If both names exist and are for different nodes, merge them */ /* If both names exist and are for different nodes, merge them */