Extended the use of "ext2spice resistor tee on" to include
DEV_RSUBCKT as well as (previously implemented) DEV_RES. The handling of DEV_RSUBCKT includes checking if the subcircuit has a substrate pin, and zeroing the capacitance to substrate for the resistor node, under the assumption that the parasitics are part of the resistor subcircuit model.
This commit is contained in:
R. Timothy Edwards
parent
fa80458d80
commit
bdc0325901
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@ -844,6 +844,8 @@ spcdevHierVisit(
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case DEV_DSUBCKT:
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case DEV_MSUBCKT:
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fprintf(esSpiceF, "%d", esSbckNum++);
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if ((dev->dev_class == DEV_RSUBCKT) && esDoResistorTee)
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fprintf(esSpiceF, "A");
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break;
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default:
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fprintf(esSpiceF, "%d", esDevNum++);
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@ -920,16 +922,27 @@ spcdevHierVisit(
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else if (dev->dev_class != DEV_MSUBCKT)
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{
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if (dev->dev_nterm > 1)
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spcdevOutNode(hc->hc_hierName, source->dterm_node->efnode_name->efnn_hier,
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spcdevOutNode(hc->hc_hierName,
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source->dterm_node->efnode_name->efnn_hier,
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"subckt", esSpiceF);
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if (dev->dev_nterm > 2)
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spcdevOutNode(hc->hc_hierName, drain->dterm_node->efnode_name->efnn_hier,
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if ((dev->dev_class == DEV_RSUBCKT) && esDoResistorTee)
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{
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/* Handle resistor "tee" model */
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spcdevOutNode(hc->hc_hierName,
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gate->dterm_node->efnode_name->efnn_hier,
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"subckt", esSpiceF);
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l /= 2; /* Halve the resistor length for each side */
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}
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else if (dev->dev_nterm > 2)
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spcdevOutNode(hc->hc_hierName,
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drain->dterm_node->efnode_name->efnn_hier,
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"subckt", esSpiceF);
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}
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else /* class DEV_MSUBCKT */
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{
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if (dev->dev_nterm > 2)
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spcdevOutNode(hc->hc_hierName, source->dterm_node->efnode_name->efnn_hier,
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spcdevOutNode(hc->hc_hierName,
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source->dterm_node->efnode_name->efnn_hier,
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"subckt", esSpiceF);
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}
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/* The following only applies to DEV_SUBCKT and DEV_VERILOGA, which */
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@ -967,6 +980,54 @@ spcdevHierVisit(
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spcHierWriteParams(hc, dev, scale, l, w, sdM, FALSE);
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if (sdM != 1.0)
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fprintf(esSpiceF, " M=%g", sdM);
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if ((dev->dev_class == DEV_RSUBCKT) && esDoResistorTee)
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{
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/* Repeat everything above for the second half of the "tee" resistor */
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fprintf(esSpiceF, "\n%c%dB", devchar, esSbckNum - 1);
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spcdevOutNode(hc->hc_hierName,
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gate->dterm_node->efnode_name->efnn_hier,
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"subckt", esSpiceF);
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spcdevOutNode(hc->hc_hierName,
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drain->dterm_node->efnode_name->efnn_hier,
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"subckt", esSpiceF);
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/* Get the device parameters now, and check if the substrate is */
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/* passed as a parameter rather than as a node. */
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plist = efGetDeviceParams(EFDevTypes[dev->dev_type]);
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for (pptr = plist; pptr != NULL; pptr = pptr->parm_next)
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if (pptr->parm_type[0] == 's')
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break;
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if ((pptr == NULL) && subnode)
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{
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EFNode *dnode;
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fprintf(esSpiceF, " ");
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subnodeFlat = spcdevSubstrate(hc->hc_hierName,
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subnode->efnode_name->efnn_hier,
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dev->dev_type, esSpiceF);
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/* If a tee resistor subcircuit has a substrate pin, then the
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* parasitic capacitance to substrate should be assumed to be
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* part of the resistor subcircuit model, and so the parasitic
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* to substrate on the "gate" node should be forced to zero.
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*/
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dnode = GetHierNode(hc, gate->dterm_node->efnode_name->efnn_hier);
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dnode->efnode_cap = 0;
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}
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/* Support for CDL format */
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if (esFormat == CDL) fprintf(esSpiceF, " /");
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fprintf(esSpiceF, " %s", EFDevTypes[dev->dev_type]);
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/* Write all requested parameters to the subcircuit call. */
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sdM = getCurDevMult();
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spcHierWriteParams(hc, dev, scale, l, w, sdM, FALSE);
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if (sdM != 1.0)
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fprintf(esSpiceF, " M=%g", sdM);
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}
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break;
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case DEV_RES:
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@ -2901,13 +2901,17 @@ spcdevVisit(
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case DEV_VOLT:
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fprintf(esSpiceF, "%d", esVoltNum++);
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break;
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case DEV_RSUBCKT:
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case DEV_SUBCKT:
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case DEV_VERILOGA:
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case DEV_RSUBCKT:
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case DEV_CSUBCKT:
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case DEV_DSUBCKT:
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case DEV_MSUBCKT:
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fprintf(esSpiceF, "%d", esSbckNum++);
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if ((dev->dev_class == DEV_RSUBCKT) && esDoResistorTee)
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/* For resistor tee networks, use, e.g., */
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/* "X1A" and "X1B", for clarity */
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fprintf(esSpiceF, "A");
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break;
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default:
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fprintf(esSpiceF, "%d", esDevNum++);
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@ -2982,7 +2986,15 @@ spcdevVisit(
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if (dev->dev_nterm > 1)
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spcdevOutNode(hierName, source->dterm_node->efnode_name->efnn_hier,
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name, esSpiceF);
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if (dev->dev_nterm > 2)
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if ((dev->dev_class == DEV_RSUBCKT) && esDoResistorTee)
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{
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l /= 2; /* Halve the resistor. Note that this may introduce
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* error if l is an odd value.
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*/
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spcdevOutNode(hierName, gate->dterm_node->efnode_name->efnn_hier,
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name, esSpiceF);
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}
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else if (dev->dev_nterm > 2)
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spcdevOutNode(hierName, drain->dterm_node->efnode_name->efnn_hier,
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name, esSpiceF);
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}
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@ -3031,6 +3043,53 @@ spcdevVisit(
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fprintf(esSpiceF, " M=%g", sdM);
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break;
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if (dev->dev_class == DEV_RSUBCKT && esDoResistorTee)
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{
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/* Write the second half of the "Tee" resistor when
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* the resistor is type DEV_RSUBCKT and not DEV_RES.
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*/
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fprintf(esSpiceF, "\n%c%dB", devchar, esSbckNum - 1);
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spcdevOutNode(hierName, gate->dterm_node->efnode_name->efnn_hier,
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name, esSpiceF);
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spcdevOutNode(hierName, drain->dterm_node->efnode_name->efnn_hier,
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name, esSpiceF);
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/* Get the device parameters now, and check if the substrate is */
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/* passed as a parameter rather than as a node. */
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plist = efGetDeviceParams(EFDevTypes[dev->dev_type]);
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for (pptr = plist; pptr != NULL; pptr = pptr->parm_next)
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if (pptr->parm_type[0] == 's')
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break;
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if ((pptr == NULL) && subnode)
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{
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fprintf(esSpiceF, " ");
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subnodeFlat = spcdevSubstrate(hierName,
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subnode->efnode_name->efnn_hier,
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dev->dev_type, esSpiceF);
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/* There is a substrate pin on the resistor subcircuit, so assume
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* that the substrate cap is part of the subcircuit model, and
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* zero it.
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*/
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gate->dterm_node->efnode_cap = 0;
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}
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/* CDL format support: Output a slash followed by a space. */
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if (esFormat == CDL) fprintf(esSpiceF, " /");
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fprintf(esSpiceF, " %s", EFDevTypes[dev->dev_type]);
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/* Write all requested parameters to the subcircuit call. */
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sdM = getCurDevMult();
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spcWriteParams(dev, hierName, scale, l, w, sdM, FALSE);
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if (sdM != 1.0)
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fprintf(esSpiceF, " M=%g", sdM);
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}
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break;
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case DEV_RES:
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if (esDoResistorTee)
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{
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