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Modified "ext2sim" behavior so that "=" statements are output 

(since these are interpreted by IRSIM, the only known program to
parse .sim output)---the "ext2sim alias on" option now just moves
such statements from the ".sim" file to a ".al" file.  Corrected the
ResSimMerge() routine to reverse the nodes, so that the devices
belonging to the aliased node are added to the original node, instead
of the other way around.  This corrects "missing gate" and "missing SD"
errors that occur due to nodes connected through the substrate.
This commit is contained in:
Tim Edwards 2021-09-13 12:25:38 -04:00
parent c7077d38c3
commit b598ce8f94
3 changed files with 29 additions and 7 deletions
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17
ext2sim/ext2sim.c
View File

@ -1603,19 +1603,32 @@ int simnodeVisit(node, res, cap)
putc('\n', esSimF);
}
if (esAliasF)
{
/* Write aliases. If the "ext2sim alias on" option was issued, then
* write to the alias file only (<name>.al). Otherwise write to the
* <name>.sim file.
*/
isGlob = EFHNIsGlob(hierName);
for (nn = node->efnode_name->efnn_next; nn; nn = nn->efnn_next)
{
if (isGlob && EFHNIsGlob(nn->efnn_hier))
continue;
if (esAliasF)
{
fprintf(esAliasF, "= ");
EFHNOut(hierName, esAliasF);
fprintf(esAliasF, " ");
EFHNOut(nn->efnn_hier, esAliasF);
fprintf(esAliasF, "\n");
}
else
{
fprintf(esSimF, "= ");
EFHNOut(hierName, esSimF);
fprintf(esSimF, " ");
EFHNOut(nn->efnn_hier, esSimF);
fprintf(esSimF, "\n");
}
}
if (esLabF)

9
extract/ExtBasic.c
View File

@ -732,17 +732,26 @@ extOutputNodes(nodeList, outFile)
/* nets. */
for (ll = reg->nreg_labels; ll; ll = ll->ll_next)
{
bool isPort = (ll->ll_attr == LL_PORTATTR) ? TRUE : FALSE;
if (ll->ll_label->lab_text == text)
{
for (ll = ll->ll_next; ll; ll = ll->ll_next)
if (extLabType(ll->ll_label->lab_text, LABTYPE_NAME))
if (strcmp(text, ll->ll_label->lab_text))
{
fprintf(outFile, "equiv \"%s\" \"%s\"\n",
text, ll->ll_label->lab_text);
if (isPort && (ll->ll_attr == LL_PORTATTR))
TxError("Warning: Ports \"%s\" and \"%s\" are"
" electrically shorted.\n",
text, ll->ll_label->lab_text);
}
break;
}
}
}
}
/*
* ---------------------------------------------------------------------

4
resis/ResReadSim.c
View File

@ -968,9 +968,9 @@ ResSimMerge(line)
TxError("Bad node alias line\n");
return(1);
}
node = ResInitializeNode(HashFind(&ResNodeTable, line[ALIASNAME]));
node = ResInitializeNode(HashFind(&ResNodeTable, line[REALNAME]));
node->status |= FORWARD;
node->forward = ResInitializeNode(HashFind(&ResNodeTable, line[REALNAME]));
node->forward = ResInitializeNode(HashFind(&ResNodeTable, line[ALIASNAME]));
node->forward->resistance += node->resistance;
node->forward->capacitance += node->capacitance;
while (node->firstDev != NULL)